sync_gen_50m.v

在显示器上显示汉字,在FPGA上实现,使用Verilog HDL 设计,完全可是直接使用

////////////////////////////////////////////////////////////////////////////////
// *****************************************************************************
// *  RICHIC CONFIDENTIAL PROPRIETARY NOTE                                     *
// *                                                                           *
// *  This software contains information confidential and proprietary to       *
// *  RicHic Inc.It shall not be reproduced in whole or in part or transferred *
// *  to other documents, or disclosed to third parties, or used for any       *
// *  purpose other than that for which it was obtained, without the prior     *
// *  written consent of RicHic Inc.                                           *
// *             (c) 2003, 2004, 2005 RicHic Inc.                              *
// *                All rights reserved                                        * 
// *****************************************************************************
//
// (C) 2004 [e-mail];     [e-mail]
//     http://www.richic.com
//
////////////////////////////////////////////////////////////////////////////////

module sync_gen_50m(
    rst_n,// synthesis attribute clock_buffer of rst_n is ibufg;
    clk,
    
    hsync,
    vsync,
    valid,
    x_cnt,
    y_cnt
    );

input           rst_n   ;
input           clk     ;

output          hsync   ;
output          vsync   ;
output          valid   ;
output  [9:0]   x_cnt   ;
output  [9:0]   y_cnt   ;

reg             hsync   ;
reg             vsync   ;
reg             valid   ;
reg     [9:0]   x_cnt   ;
reg     [9:0]   y_cnt   ;

always @ ( posedge clk or negedge rst_n )
    if ( !rst_n )
        x_cnt <= 10'd0;
    else if ( x_cnt == 10'd1000 )
        x_cnt <= 10'd0;
    else
        x_cnt <= x_cnt + 1'b1;
        
always @ ( posedge clk or negedge rst_n )
    if ( !rst_n )
        y_cnt <= 10'd0;
    else if ( y_cnt == 10'd665 )
        y_cnt <= 10'd0;    
    else if ( x_cnt == 10'd1000 )
        y_cnt <= y_cnt + 1'b1;    
        
always @ ( posedge clk or negedge rst_n )
    if ( !rst_n )
        begin
            hsync <= 1'b0;
            vsync <= 1'b0;
        end
    else
        begin
            hsync <= x_cnt <= 10'd50;
            vsync <= y_cnt <= 10'd6;
        end    

always @ ( posedge clk or negedge rst_n )                     
    if ( !rst_n )
        valid <= 1'b0;
    else
        valid <=    ( ( x_cnt > 10'd180 ) && ( x_cnt < 10'd980) &&
                      ( y_cnt > 10'd35)   && ( y_cnt < 10'd635) ); 
                    
endmodule