📄 sin.rpt
字号:
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GNDIO
VCCINT | 6 103 | GNDINT
f2 | 7 102 | f12
f0 | 8 101 | f4
RESERVED | 9 100 | f3
RESERVED | 10 99 | RESERVED
RESERVED | 11 98 | RESERVED
RESERVED | 12 97 | RESERVED
RESERVED | 13 96 | RESERVED
RESERVED | 14 95 | RESERVED
GNDIO | 15 94 | VCCIO
GNDINT | 16 93 | VCCINT
p6b1 | 17 92 | RESERVED
fout6 | 18 91 | RESERVED
p6b0 | 19 EPF10K20TC144-4 90 | RESERVED
fout2 | 20 89 | fout7
fout4 | 21 88 | fout1
fout0 | 22 87 | RESERVED
fout5 | 23 86 | f11
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
f10 | 26 83 | f8
f5 | 27 82 | f9
f7 | 28 81 | RESERVED
f6 | 29 80 | RESERVED
RESERVED | 30 79 | RESERVED
fout3 | 31 78 | RESERVED
RESERVED | 32 77 | ^MSEL0
RESERVED | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
RESERVED | 36 73 | RESERVED
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
R R R G R R R R V R R R R G R V V c c c G G R R V f R p R G R R R R V R
E E E N E E E E C E E E E N E C C l l l N N E E C 1 E 6 E N E E E E C E
S S S D S S S S C S S S S D S C C k k k D D S S C 3 S b S D S S S S C S
E E E I E E E E I E E E E I E I I 3 0 I I E E I E 2 E I E E E E I E
R R R O R R R R O R R R R O R N N N N R R O R R O R R R R O R
V V V V V V V V V V V V T T T T V V V V V V V V V
E E E E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: f:\sin\sin.rpt
sin
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A2 7/ 8( 87%) 3/ 8( 37%) 2/ 8( 25%) 2/2 0/2 7/22( 31%)
A3 8/ 8(100%) 4/ 8( 50%) 2/ 8( 25%) 0/2 0/2 8/22( 36%)
A4 5/ 8( 62%) 1/ 8( 12%) 5/ 8( 62%) 0/2 0/2 6/22( 27%)
A6 5/ 8( 62%) 3/ 8( 37%) 4/ 8( 50%) 1/2 0/2 3/22( 13%)
A7 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 0/2 5/22( 22%)
A8 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 1/2 0/2 1/22( 4%)
A9 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 7/22( 31%)
A10 4/ 8( 50%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
A12 8/ 8(100%) 1/ 8( 12%) 6/ 8( 75%) 1/2 0/2 2/22( 9%)
B1 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 11/22( 50%)
B2 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 8/22( 36%)
B3 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 7/22( 31%)
B4 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 9/22( 40%)
B5 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
B6 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 6/22( 27%)
B7 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 6/22( 27%)
B8 7/ 8( 87%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 7/22( 31%)
B9 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 9/22( 40%)
B10 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 7/22( 31%)
B11 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 0/2 0/2 7/22( 31%)
B12 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 0/2 0/2 7/22( 31%)
B13 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 6/22( 27%)
B14 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 6/22( 27%)
B15 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 8/22( 36%)
B16 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 6/22( 27%)
B17 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 4/22( 18%)
B18 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 5/22( 22%)
B19 7/ 8( 87%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 6/22( 27%)
B20 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 7/22( 31%)
B21 3/ 8( 37%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 2/22( 9%)
B22 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 0/2 0/2 7/22( 31%)
B23 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 6/22( 27%)
B24 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 8/22( 36%)
C1 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
C4 7/ 8( 87%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 6/22( 27%)
C6 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 8/22( 36%)
C7 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 7/22( 31%)
C8 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 9/22( 40%)
C9 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 5/22( 22%)
C11 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 0/2 0/2 7/22( 31%)
C12 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
C13 3/ 8( 37%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 2/22( 9%)
C15 8/ 8(100%) 4/ 8( 50%) 3/ 8( 37%) 0/2 0/2 6/22( 27%)
C16 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 6/22( 27%)
C17 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 9/22( 40%)
C19 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 0/2 0/2 6/22( 27%)
C20 8/ 8(100%) 4/ 8( 50%) 0/ 8( 0%) 0/2 0/2 9/22( 40%)
C21 3/ 8( 37%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 2/22( 9%)
C23 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 6/22( 27%)
C24 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
D1 5/ 8( 62%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 6/22( 27%)
D2 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 0/22( 0%)
D5 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
D6 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 5/22( 22%)
D10 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 5/22( 22%)
E1 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 2/2 0/2 13/22( 59%)
E2 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 5/22( 22%)
E3 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 10/22( 45%)
E4 8/ 8(100%) 5/ 8( 62%) 1/ 8( 12%) 0/2 0/2 9/22( 40%)
E5 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 8/22( 36%)
E6 4/ 8( 50%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 6/22( 27%)
E7 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 1/2 0/2 5/22( 22%)
E8 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 5/22( 22%)
E9 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 11/22( 50%)
E10 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 3/22( 13%)
E11 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 5/22( 22%)
E12 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 9/22( 40%)
E13 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 3/22( 13%)
E16 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 8/22( 36%)
E18 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 1/2 0/2 4/22( 18%)
E19 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 3/22( 13%)
E20 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
E21 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 5/22( 22%)
E22 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 1/22( 4%)
E23 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 1/2 0/2 1/22( 4%)
F1 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 7/22( 31%)
F2 2/ 8( 25%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
F3 3/ 8( 37%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 2/22( 9%)
F4 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 6/22( 27%)
F6 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 9/22( 40%)
F7 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 9/22( 40%)
F9 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 5/22( 22%)
F10 7/ 8( 87%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 7/22( 31%)
F12 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
F13 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 6/22( 27%)
F14 7/ 8( 87%) 3/ 8( 37%) 1/ 8( 12%) 0/2 0/2 5/22( 22%)
F15 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 9/22( 40%)
F16 8/ 8(100%) 4/ 8( 50%) 2/ 8( 25%) 0/2 0/2 6/22( 27%)
F17 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 7/22( 31%)
F18 6/ 8( 75%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 7/22( 31%)
F19 7/ 8( 87%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 6/22( 27%)
F20 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 6/22( 27%)
F21 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 9/22( 40%)
F22 7/ 8( 87%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 6/22( 27%)
F23 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 0/2 0/2 7/22( 31%)
F24 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 0/2 0/2 8/22( 36%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
D25 8/8 (100%) 2/8 ( 25%) 6/8 ( 75%) 0/2 2/2 6/22( 27%)
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 30/96 ( 31%)
Total logic cells used: 648/1152 ( 56%)
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