sin.rpt
来自「dds信号发生器」· RPT 代码 · 共 913 行 · 第 1/5 页
RPT
913 行
Total embedded cells used: 8/48 ( 16%)
Total EABs used: 1/6 ( 16%)
Average fan-in: 3.10/4 ( 77%)
Total fan-in: 2013/4608 ( 43%)
Total input pins required: 12
Total input I/O cell registers required: 0
Total output pins required: 24
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 648
Total flipflops required: 92
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 18/1152 ( 1%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 7 8 5 0 5 8 8 8 4 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 61/0
B: 8 8 8 8 1 8 8 7 8 8 8 8 0 8 8 7 8 2 8 7 8 3 8 8 8 171/0
C: 1 0 0 7 0 8 8 8 8 0 8 1 0 3 0 8 8 8 0 8 8 3 0 8 8 111/0
D: 5 1 0 0 1 8 0 0 0 8 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 23/8
E: 8 8 8 8 8 4 8 8 8 8 8 8 0 2 0 0 8 0 8 2 2 8 8 8 0 138/0
F: 8 2 3 8 0 8 7 0 8 7 0 2 0 8 7 8 8 8 6 7 8 8 7 8 8 144/0
Total: 30 26 27 36 10 41 39 31 40 35 24 27 8 21 15 23 32 18 22 24 26 22 23 32 24 648/8
Device-Specific Information: f:\sin\sin.rpt
sin
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
55 - - - -- INPUT G 0 0 0 0 clk
56 - - - -- INPUT G 0 0 0 0 clk0
124 - - - -- INPUT G 0 0 0 0 clk1
125 - - - -- INPUT G 0 0 0 0 clk2
54 - - - -- INPUT G 0 0 0 0 clk3
19 - - D -- INPUT 0 0 0 3 p6b0
17 - - D -- INPUT 0 0 0 2 p6b1
64 - - - 09 INPUT 0 0 0 2 p6b2
110 - - - 01 INPUT 0 0 0 2 p6b3
112 - - - 02 INPUT 0 0 0 2 p6b4
118 - - - 06 INPUT 0 0 0 1 p6b5
126 - - - -- INPUT 0 0 0 52 q1in
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\sin\sin.rpt
sin
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
22 - - D -- OUTPUT 0 1 0 0 fout0
88 - - D -- OUTPUT 0 1 0 0 fout1
20 - - D -- OUTPUT 0 1 0 0 fout2
31 - - F -- OUTPUT 0 1 0 0 fout3
21 - - D -- OUTPUT 0 1 0 0 fout4
23 - - D -- OUTPUT 0 1 0 0 fout5
18 - - D -- OUTPUT 0 1 0 0 fout6
89 - - C -- OUTPUT 0 1 0 0 fout7
8 - - A -- OUTPUT 0 1 0 0 f0
109 - - A -- OUTPUT 0 1 0 0 f1
7 - - A -- OUTPUT 0 1 0 0 f2
100 - - A -- OUTPUT 0 1 0 0 f3
101 - - A -- OUTPUT 0 1 0 0 f4
27 - - E -- OUTPUT 0 1 0 0 f5
29 - - E -- OUTPUT 0 1 0 0 f6
28 - - E -- OUTPUT 0 1 0 0 f7
83 - - E -- OUTPUT 0 1 0 0 f8
82 - - E -- OUTPUT 0 1 0 0 f9
26 - - E -- OUTPUT 0 1 0 0 f10
86 - - E -- OUTPUT 0 1 0 0 f11
102 - - A -- OUTPUT 0 1 0 0 f12
62 - - - 11 OUTPUT 0 0 0 0 f13
111 - - - 01 OUTPUT 0 0 0 0 f14
116 - - - 04 OUTPUT 0 0 0 0 f15
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\sin\sin.rpt
sin
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - D 01 OR2 2 2 0 2 |ADDER6B:23|LPM_ADD_SUB:19|addcore:adder|pcarry1
- 1 - D 01 OR2 1 2 0 2 |ADDER6B:23|LPM_ADD_SUB:19|addcore:adder|pcarry2
- 8 - D 10 OR2 1 2 0 2 |ADDER6B:23|LPM_ADD_SUB:19|addcore:adder|pcarry3
- 7 - D 10 OR2 s 1 1 0 1 |ADDER6B:23|LPM_ADD_SUB:19|addcore:adder|~92~1
- 7 - B 10 OR2 1 3 0 2 |ADDER26B:37|LPM_ADD_SUB:91|addcore:adder|pcarry1
- 2 - B 10 OR2 1 3 0 2 |ADDER26B:37|LPM_ADD_SUB:91|addcore:adder|pcarry2
- 3 - B 23 OR2 1 3 0 2 |ADDER26B:37|LPM_ADD_SUB:91|addcore:adder|pcarry3
- 5 - B 23 OR2 1 3 0 2 |ADDER26B:37|LPM_ADD_SUB:91|addcore:adder|pcarry4
- 7 - B 23 OR2 1 3 0 2 |ADDER26B:37|LPM_ADD_SUB:91|addcore:adder|pcarry5
- 1 - B 23 OR2 1 3 0 2 |ADDER26B:37|LPM_ADD_SUB:91|addcore:adder|pcarry6
- 2 - B 13 OR2 1 3 0 2 |ADDER26B:37|LPM_ADD_SUB:91|addcore:adder|pcarry7
- 5 - B 13 OR2 1 3 0 2 |ADDER26B:37|LPM_ADD_SUB:91|addcore:adder|pcarry8
- 7 - B 13 OR2 1 3 0 2 |ADDER26B:37|LPM_ADD_SUB:91|addcore:adder|pcarry9
- 4 - B 13 OR2 1 3 0 2 |ADDER26B:37|LPM_ADD_SUB:91|addcore:adder|pcarry10
- 3 - F 13 OR2 1 3 0 2 |ADDER26B:37|LPM_ADD_SUB:91|addcore:adder|pcarry11
- 5 - F 13 OR2 1 3 0 2 |ADDER26B:37|LPM_ADD_SUB:91|addcore:adder|pcarry12
- 7 - F 13 OR2 1 3 0 2 |ADDER26B:37|LPM_ADD_SUB:91|addcore:adder|pcarry13
- 1 - F 13 OR2 1 3 0 2 |ADDER26B:37|LPM_ADD_SUB:91|addcore:adder|pcarry14
- 3 - F 20 OR2 1 3 0 2 |ADDER26B:37|LPM_ADD_SUB:91|addcore:adder|pcarry15
- 5 - F 20 OR2 1 3 0 2 |ADDER26B:37|LPM_ADD_SUB:91|addcore:adder|pcarry16
- 7 - F 20 OR2 1 3 0 2 |ADDER26B:37|LPM_ADD_SUB:91|addcore:adder|pcarry17
- 1 - F 20 OR2 1 3 0 2 |ADDER26B:37|LPM_ADD_SUB:91|addcore:adder|pcarry18
- 2 - C 23 OR2 1 3 0 2 |ADDER26B:37|LPM_ADD_SUB:91|addcore:adder|pcarry19
- 4 - C 23 OR2 1 3 0 2 |ADDER26B:37|LPM_ADD_SUB:91|addcore:adder|pcarry20
- 6 - C 23 OR2 1 3 0 2 |ADDER26B:37|LPM_ADD_SUB:91|addcore:adder|pcarry21
- 7 - C 23 OR2 1 3 0 2 |ADDER26B:37|LPM_ADD_SUB:91|addcore:adder|pcarry22
- 5 - D 06 OR2 1 3 0 2 |ADDER26B:37|LPM_ADD_SUB:91|addcore:adder|pcarry23
- 7 - D 06 OR2 1 3 0 3 |ADDER26B:37|LPM_ADD_SUB:91|addcore:adder|pcarry24
- 4 - B 10 OR2 1 3 0 2 |ADDER26B:37|LPM_ADD_SUB:91|addcore:adder|:152
- 4 - D 06 OR2 0 4 0 3 |ADDER26B:37|LPM_ADD_SUB:91|addcore:adder|:259
- 3 - A 03 OR2 ! 0 3 0 3 |DIVIDE:4|lpm_add_sub:159|addcore:adder|:99
- 8 - E 04 OR2 ! 0 3 0 2 |DIVIDE:4|lpm_add_sub:159|addcore:adder|:107
- 5 - E 04 OR2 ! 0 4 0 2 |DIVIDE:4|lpm_add_sub:159|addcore:adder|:119
- 1 - E 09 OR2 ! 0 2 0 11 |DIVIDE:4|lpm_add_sub:159|addcore:adder|:123
- 5 - C 06 OR2 0 2 0 1 |DIVIDE:4|lpm_add_sub:205|addcore:adder|pcarry5
- 1 - C 11 OR2 0 4 0 12 |DIVIDE:4|lpm_add_sub:205|addcore:adder|pcarry11
- 4 - A 02 OR2 0 3 0 4 |DIVIDE:4|lpm_add_sub:205|addcore:adder|:99
- 1 - C 06 OR2 0 3 0 2 |DIVIDE:4|lpm_add_sub:205|addcore:adder|:107
- 4 - C 11 OR2 0 3 0 3 |DIVIDE:4|lpm_add_sub:205|addcore:adder|:115
- 5 - C 08 OR2 0 2 0 1 |DIVIDE:4|lpm_add_sub:251|addcore:adder|pcarry5
- 8 - C 11 OR2 0 4 0 12 |DIVIDE:4|lpm_add_sub:251|addcore:adder|pcarry11
- 4 - C 09 OR2 0 3 0 4 |DIVIDE:4|lpm_add_sub:251|addcore:adder|:99
- 4 - C 06 OR2 0 3 0 2 |DIVIDE:4|lpm_add_sub:251|addcore:adder|:107
- 3 - C 06 OR2 0 3 0 3 |DIVIDE:4|lpm_add_sub:251|addcore:adder|:115
- 5 - C 07 OR2 0 2 0 1 |DIVIDE:4|lpm_add_sub:297|addcore:adder|pcarry5
- 1 - C 04 OR2 0 4 0 12 |DIVIDE:4|lpm_add_sub:297|addcore:adder|pcarry11
- 5 - C 17 OR2 0 3 0 4 |DIVIDE:4|lpm_add_sub:297|addcore:adder|:99
- 7 - C 08 OR2 0 3 0 2 |DIVIDE:4|lpm_add_sub:297|addcore:adder|:107
- 2 - C 08 OR2 0 3 0 3 |DIVIDE:4|lpm_add_sub:297|addcore:adder|:115
- 6 - C 17 OR2 0 2 0 4 |DIVIDE:4|lpm_add_sub:343|addcore:adder|pcarry5
- 2 - C 04 OR2 0 4 0 12 |DIVIDE:4|lpm_add_sub:343|addcore:adder|pcarry11
- 2 - C 16 OR2 0 3 0 2 |DIVIDE:4|lpm_add_sub:343|addcore:adder|:99
- 8 - C 07 AND2 0 2 0 1 |DIVIDE:4|lpm_add_sub:343|addcore:adder|:107
- 1 - C 07 OR2 0 4 0 3 |DIVIDE:4|lpm_add_sub:343|addcore:adder|:115
- 1 - C 19 OR2 0 4 0 12 |DIVIDE:4|lpm_add_sub:389|addcore:adder|pcarry11
- 3 - C 16 OR2 0 3 0 3 |DIVIDE:4|lpm_add_sub:389|addcore:adder|:99
- 3 - C 17 OR2 0 3 0 3 |DIVIDE:4|lpm_add_sub:389|addcore:adder|:107
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