scc2.v

来自「完整的jpeg encoder verilog code,DCT部分採用1991」· Verilog 代码 · 共 35 行

`timescale 1ns/10ps     
`define bw  12          
//scc42 skew-circular convolution                         
module scc2(//input         
               nrst,clk,
               scc2en,
               scc2en_d,
               di,  
             //output        
               do);          
input  nrst,clk;
input  scc2en,scc2en_d;
input  [`bw-1:0] di;
output [`bw-1:0] do;

reg  [`bw-1:0] sccreg1, sccreg2;
wire [`bw-1:0] sccreg_in=scc2en?di:sccreg2;

wire sccreg1en= scc2en | scc2en_d;
always @(posedge clk or negedge nrst)
 if (~nrst)         sccreg1<=0;
 else if (sccreg1en)sccreg1<=sccreg_in;
 
wire scc2en_n=~scc2en & scc2en_d;
always @(posedge clk or negedge nrst)
 if (~nrst)         sccreg2<=0;
 else if (scc2en_n) sccreg2<=~sccreg1+1;
 else if (scc2en_d) sccreg2<= sccreg1;
// else               sccreg2<=0;

//==============================================================================================================
// multiplier part              
//0.1913417 multiplier                       
wire [`bw-1:0] csa4_2= sccreg1;
wire [`bw-1:0] csa4_3=(sccreg1[`bw-1]==1)? {2'b0,~sccreg1[`bw-1:2]}:{2'b11,~sccreg1[`bw-1:2]}; //csa4_3琌璽