scc4.v

来自「完整的jpeg encoder verilog code,DCT部分採用1991」· Verilog 代码 · 共 35 行

`timescale 1ns/10ps
`define bw  12    
//use 12 flip flop 

module scc4(//input
               nrst,clk,
               dcten,idcten,
               
               scc4en,scc4en_d,
               
               a0en,a1en,a2en,a3en,
               a4en,a5en,a6en,a7en,
               sub1en,sub2en,sub3en,sub4en,
               di,
               a0,a1,a2,a3,a4,a5,a6,a7,
             //output               
               do);
               
input  nrst,clk;
input  dcten,idcten;
input  scc4en,scc4en_d;    
input  a0en,a1en,a2en,a3en;   
input  a4en,a5en,a6en,a7en;   
input  sub1en,sub2en,sub3en,sub4en;    
    
input  [`bw-1:0] di; 
output [`bw-1:0] a0,a1,a2,a3,a4,a5,a6,a7;                           
output [`bw-1:0] do;    

reg [`bw-1:0] a0,a0_d,a1,a1_d,a2,a3,a4,a5,a6,a7;
always @(posedge clk or negedge nrst)
 if (~nrst) begin
    a0<=0; a1<=0; a2<=0; a3<=0;
    a4<=0; a5<=0; a6<=0; a7<=0;
 end else begin //2 4 5 7