add.v

来自「完整的jpeg encoder verilog code,DCT部分採用1991」· Verilog 代码 · 共 9 行

`timescale 1ns/10ps
`define bw 12
module add(a1,a2,sum);
input  [`bw-1:0] a1,a2;
output [`bw-1:0] sum;

wire [`bw-1:0] sum=a1+a2;

endmodule