transram64.v

来自「完整的jpeg encoder verilog code,DCT部分採用1991」· Verilog 代码 · 共 29 行

`timescale 1ns/10ps   
`define depth 64
`define width  16
module transram64 (//input
             CLK,CEN,
             WEN,A,     
             D,
             
             //output
             Q);                         
input  CLK,CEN,WEN;
input  [5:0] A;
input  [`width-1:0] D;

output [`width-1:0] Q;
          
reg [`width-1:0] mem[0:`depth-1];            

always@(posedge CLK)
begin
 if (~WEN&~CEN)  mem[A]<=D;
end 
reg [5:0] rptr;
always@(posedge CLK) rptr<=#1 A;

wire [`width-1:0]  Q=~CEN?mem[rptr]:8'bZ; 
 
endmodule