vlcctl.v

完整的jpeg encoder verilog code,DCT部分採用1991 IEEE transection paper,利用skew circular convolution來實現精簡電路

`timescale 1ns/10ps
//
//
//
module vlcctl(//input                                                                                                           
               clk,nrst,
               dcten,
               dqin,den,                                                                                                            
               lumenb,chromenb, 
               
              //output
               idle,dc,eob,dcsize,
               zero15,
               vlcdeno,unsg_dout,sign,
               lrun,lsize,
               crun,csize);                                                                                             
                                                                    
input        clk,nrst;     
input        dcten;
input  [7:0] dqin;                              
input        den;              
input        lumenb,chromenb;           

output       idle;
output       dc,eob;
output [3:0] dcsize;
output       zero15;
output       vlcdeno;              
output [7:0] unsg_dout;   //for appended code word 
output       sign;
output [3:0] lrun,lsize; 
output [3:0] crun,csize;

reg  [7:0] run_tmp,run;                                  
wire #1 zero= den&(dqin==0);     

wire [3:0] size;
reg  [7:0] prev_dc;

reg  den_d;
reg  lumenb_d,chromenb_d;
wire zero15=(run==14);
wire idle=(zero& ~zero15);
//for successively 15 zero add a codeword!
always @(posedge clk or negedge nrst)
 if (~nrst)             run<=0; 
 else if (~zero|zero15) run<=0;
 else if ( zero)        run<=run+1;
     
always @(posedge clk or negedge nrst)
 if (~nrst)  den_d <=0;
 else        den_d <=den; 

wire vlcdeno= den ; 
wire dc     = den &~den_d;
wire eob    =~den & den_d;   

always @(posedge clk or negedge nrst)
 if (~nrst) begin
              lumenb_d<=0;
              chromenb_d<=0;
 end else begin
              lumenb_d<=lumenb;
              chromenb_d<=chromenb;    
 end             
 
wire change=(~lumenb&lumenb_d)|(~chromenb&chromenb_d);     
//while luminance change to chrominance
// prev_dc value reset
always @(posedge clk or negedge nrst)
 if (~nrst)              prev_dc<=0;
 else if (~dcten|change) prev_dc<=0;
 else if (dc)            prev_dc<=dqin;       
 
wire [7:0] dcdiff= dc?(dqin - prev_dc):0;
wire [7:0] unsigned_dcdiff=dcdiff[7]?(~dcdiff+1):dcdiff;
//wire [7:0] dc_append=dcdiff[7]?(~dcdiff):dcdiff;
//wire [7:0] ac_appended=dqin[7]?(~dqin):dqin;

wire [7:0] unsigned_ac=dqin[7]?(~dqin+1):dqin;    
wire [7:0] unsigned_din=dc? unsigned_dcdiff : unsigned_ac; 
// need second unsigned part
wire [7:0] unsg_dout=unsigned_din;//dc? dc_append:ac_appended;                       
wire sign   =dc? dcdiff[7]: dqin[7];

sizetable sizetable(
          //input
            .din(unsigned_din),
          //output
            .size(size)); 
            
wire [3:0] dcsize=dc?size:0;          
wire [3:0] lsize=lumenb?size:0;
wire [3:0] csize=chromenb?size:0;
wire [3:0] lrun =lumenb?(zero15?(run+1):run):0;
wire [3:0] crun =chromenb?run:0;                        
                                                                                                                                
endmodule