fa0.v

完整的jpeg encoder verilog code,DCT部分採用1991 IEEE transection paper,利用skew circular convolution來實現精簡電路

`timescale 1ns/10ps
module FA0(x,y,z,s,c);
input x,y,z;
output s,c;

wire s=x ^ y ^ z;
wire c=x & y | z & (x | y);

endmodule