dctctl.v

来自「完整的jpeg encoder verilog code,DCT部分採用1991」· Verilog 代码 · 共 27 行

`timescale 1ns/10ps     
`define bw  12

module dctctl(//input
              nrst,clk,
              dcten,idcten,
              //output
              transin,   //transpose input rather than source input
              octcntr,cntr,
              wen,addr );             

input        nrst,clk;
input        dcten,idcten;

output       transin; 
output [3:0] octcntr;      
output [3:0] cntr;
output       wen;
output [5:0] addr;
//==========================================================
// signal declaration
// 
reg [2:0] subcntr;
reg trans_tmp;
reg [3:0] cntr;
//==========================================================
//