csa4.v

来自「完整的jpeg encoder verilog code,DCT部分採用1991」· Verilog 代码 · 共 49 行

`timescale 1ns/10ps
`define width 13 

module csa4(//input
             a1,a2,a3,a4,

            //output
             sum);
input  [`width-2:0] a1,a2,a3,a4;
output [`width:0] sum;


wire [`width:0] c_tmp;
wire [`width:0] s_tmp;

wire [`width:0] a1m=(a1[`width-2]==1)?{2'b11,a1}:{2'b0,a1};
wire [`width:0] a2m=(a2[`width-2]==1)?{2'b11,a2}:{2'b0,a2};
wire [`width:0] a3m=(a3[`width-2]==1)?{2'b11,a3}:{2'b0,a3};
wire [`width:0] a4m=(a4[`width-2]==1)?{2'b11,a4}:{2'b0,a4};

assign s_tmp=a1m ^ a2m ^ a3m;
assign c_tmp=(a1m & a2m) | (a1m & a3m) | (a2m & a3m);

//
wire [`width:0] c_tmp1={c_tmp,1'b0};
wire [`width:0] s_tmp1={1'b0,s_tmp};
wire [`width:0] a4_tmp=a4m[`width:0];

wire [`width:0] c_tmp2;
wire [`width:0] s_tmp2;

assign s_tmp2= s_tmp1 ^ c_tmp1 ^ a4_tmp;
assign c_tmp2= (s_tmp1 & c_tmp1) | (s_tmp1 & a4_tmp) | (c_tmp1 & a4_tmp);


wire [`width:0] c_tmp3={c_tmp2,1'b0};
wire [`width:0] s_tmp3={1'b0,s_tmp2};
wire [`width:0] sum=c_tmp3+s_tmp3;



endmodule