sfifo.v

来自「完整的jpeg encoder verilog code,DCT部分採用1991」· Verilog 代码 · 共 32 行

`timescale 1ns/10ps   
`define depth 64
`define width  8
module sfifo(//input
             clk,cen,
             wen,wptr,rptr,            
             din,
             
             //output
             dout);                         
input  clk,cen,wen;
input  [5:0] wptr,rptr;
input  [`width-1:0] din;

output [`width-1:0] dout;

reg [`width-1:0] dout;            
reg [`width-1:0] mem[0:`depth-1];            

always@(negedge clk)
 if (wen&~cen)  mem[wptr]<=din;

wire [7:0] test0=mem[0];
wire [7:0] test1=mem[1];
wire [7:0] test2=mem[2];   
wire [7:0] test3=mem[3];   

wire [7:0] #1 dout_tmp=mem[rptr]; 
always@(posedge clk)  
 dout<=dout_tmp;   
                        
endmodule