zzscan.v

完整的jpeg encoder verilog code,DCT部分採用1991 IEEE transection paper,利用skew circular convolution來實現精簡電路

`timescale 1ns/10ps
//===================================================
// The function of this module is to generate the
// zzig zag scan read ptr
//===================================================
module zzscan(//input
               clk,nrst,                                                       
               qen,qenstop,
               dcten,
               //output
               dqptr,
               vlcden);
               
input clk;
input nrst;
input qen,qenstop,dcten;

output [5:0] dqptr;
output vlcden;      

wire switchen,switchdis;                                       
reg  switch,lrchange;                                           
reg [2:0] icntr,uplimit;                                       
always @(posedge clk or negedge nrst)                          
 if (~nrst)               icntr<=#1 0;                         
 else if (~qen&dcten)                                          
      if (icntr==uplimit) icntr<=#1 0;                         
      else                icntr<=#1 icntr+1;                   
 else icntr<=0;                                                
                                                               
wire #1 uplimit_up=(~switch)&(icntr==uplimit);                 
wire #1 uplimit_dn=(switchen|switch)&(icntr==uplimit);         
always @(posedge clk or negedge nrst)                          
 if (~nrst)                uplimit<=#1 1;                      
 else if (~qen&dcten)                                          
      if (switchdis)       uplimit<=#1 1;                      
      else if (uplimit_dn) uplimit<=#1 uplimit-1;              
      else if (uplimit_up) uplimit<=#1 uplimit+1;              
      else                 uplimit<=#1 uplimit;                
 else                      uplimit<=#1 1;                      
                                                               
assign switchen=(uplimit==7)&(icntr==7);                       
assign switchdis=(uplimit==0)&(icntr==0);                      
always @(posedge clk or negedge nrst)                          
 if (~nrst)              switch<=#1 0;                         
 else if (~qen&dcten)                                          
      if (switchdis)     switch<=#1 0;                         
      else if (switchen) switch<=#1 1;                         
      else               switch<=#1 switch;                    
 else                    switch<=#1 0;                         
                                                               
wire lrchange_en=uplimit_up|uplimit_dn;                        
always @(posedge clk or negedge nrst)                          
 if (~nrst)           lrchange<=0;                             
 else if (~qen&dcten)                                          
      if (lrchange_en)lrchange<=~lrchange;                     
      else            lrchange<= lrchange;                     
 else                 lrchange<=0;                          
                                                               
wire [2:0] ptr1=uplimit-icntr;  
wire [2:0] ptr2=uplimit-ptr1;                                
wire [2:0] ptr11=~switch? ptr1:(7-uplimit+ptr1); 
wire [2:0] ptr22=~switch? ptr2:(7-uplimit+ptr2);
                                                               
wire [2:0] lptr=~lrchange?ptr22:ptr11;                         
wire [2:0] rptr= lrchange?ptr22:ptr11;                         
wire [5:0] dqptr_tmp=qenstop? 0: {rptr,3'b0} + lptr;   

reg  [5:0] dqptr;
always @(posedge clk or negedge nrst)
 if (~nrst) dqptr<=0;
 else       dqptr<=dqptr_tmp;
 
reg vlcden;
always @(posedge clk or negedge nrst)
 if (~nrst) vlcden<=0;
 else       vlcden<=qen;
                        
endmodule