jpegctl.v

来自「完整的jpeg encoder verilog code,DCT部分採用1991」· Verilog 代码 · 共 37 行

`timescale 1ns/10ps
`define bw  12
module jpegctl(
        //input
         clk,nrst,
         octcntr,cntr,
         dcten,
         transin,transout,
         dinran,dout,dctdiv,  
         //qrptr,
         dqptr,  
        //output
         din,
         qram64_wen,         
         qram64_addr,dq_addr,dqout,
         dctout,qen,qenstop
         
        );
input        clk,nrst;
input  [3:0]  octcntr;
input  [3:0]  cntr;
input         dcten;
input         transin,transout;
input  [11:0] dinran,dout; 
input  [`bw+5:0] dctdiv;
//input  [5:0]  qrptr;       
input  [5:0]  dqptr; 
               
output [11:0] din; 
output        qram64_wen;
output [5:0]  qram64_addr,dq_addr;
output [5:0]  dqout;
output [`bw-1:0] dctout;
output        qen,qenstop;

//=======================================================  
//讽2D-DCT暗Ч