📄 i2c_slave.mpf
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; if assertion triggers a breakpoint (controlled by BreakOnAssertion level),; otherwise use AssertionFormat.;; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"; AssertionFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"; AssertionFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n"; AssertionFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n"; AssertionFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"; AssertionFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"; AssertionFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"; Assertion File - alternate file for storing VHDL/PSL assertion messages; AssertFile = assert.log; Default radix for all windows and commands.; Set to symbolic, ascii, binary, octal, decimal, hex, unsignedDefaultRadix = symbolic; VSIM Startup command; Startup = do startup.do; File for saving command transcript;TranscriptFile = transcript; File for saving command history; CommandHistory = cmdhist.log; Specify whether paths in simulator commands should be described; in VHDL or Verilog format.; For VHDL, PathSeparator = /; For Verilog, PathSeparator = .; Must not be the same character as DatasetSeparator.PathSeparator = /; Specify the dataset separator for fully rooted contexts.; The default is ':'. For example: sim:/top; Must not be the same character as PathSeparator.DatasetSeparator = :; Disable VHDL assertion messages; IgnoreNote = 1; IgnoreWarning = 1; IgnoreError = 1; IgnoreFailure = 1; Default force kind. May be freeze, drive, or deposit; or in other terms, fixed, wired, or charged.; DefaultForceKind = freeze; If zero, open files when elaborated; otherwise, open files on; first read or write. Default is 0.; DelayFileOpen = 1; Control VHDL files opened for write.; 0 = Buffered, 1 = UnbufferedUnbufferedOutput = 0; Control the number of VHDL files open concurrently.; This number should always be less than the current ulimit; setting for max file descriptors.; 0 = unlimitedConcurrentFileLimit = 40; Control the number of hierarchical regions displayed as; part of a signal name shown in the Wave window.; A value of zero tells VSIM to display the full name.; The default is 0.; WaveSignalNameWidth = 0; Turn off warnings from the std_logic_arith, std_logic_unsigned; and std_logic_signed packages. StdArithNoWarnings = 1; Turn off warnings from the IEEE numeric_std and numeric_bit packages. NumericStdNoWarnings = 1; Control the format of a generate statement label. Do not quote it.; GenerateFormat = %s__%d; Specify whether checkpoint files should be compressed.; The default is 1 (compressed).; CheckpointCompressMode = 0; List of dynamically loaded objects for Verilog PLI applications; Veriuser = veriuser.sl; Specify default options for the restart command. Options can be one; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions; DefaultRestartOptions = -force; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs; (> 500 megabyte memory footprint). Default is disabled.; Specify number of megabytes to lock.; LockedMemory = 1000; HP-UX 11.00 ONLY - Use /usr/lib/libCsup_v2.sl for shared object loading.; This is necessary when C++ files have been compiled with aCC's -AA option.; The default behavior is to use /usr/lib/libCsup.sl.; UseCsupV2 = 1; Turn on (1) or off (0) WLF file compression.; The default is 1 (compress WLF file).; WLFCompress = 0; Specify whether to save all design hierarchy (1) in the WLF file; or only regions containing logged signals (0).; The default is 0 (log only regions with logged signals).; WLFSaveAllRegions = 1; WLF file time limit. Limit WLF file by time, as closely as possible,; to the specified amount of simulation time. When the limit is exceeded; the earliest times get truncated from the file.; If both time and size limits are specified the most restrictive is used.; UserTimeUnits are used if time units are not specified.; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}; WLFTimeLimit = 0; WLF file size limit. Limit WLF file size, as closely as possible,; to the specified number of megabytes. If both time and size limits; are specified then the most restrictive is used.; The default is 0 (no limit).; WLFSizeLimit = 1000; Specify whether or not a WLF file should be deleted when the; simulation ends. A value of 1 will cause the WLF file to be deleted.; The default is 0 (do not delete WLF file when simulation ends).; WLFDeleteOnQuit = 1; Specify whether or not a WLF file should be optimized during ; simulation. If set to 0, the WLF file will not be optimized.; The default is 1, optimize the WLF file.; WLFOptimize = 0; Specify whether or not integer arrays will appear as memories.; The default is 1 (display integer arrays as memories).; ShowIntMem = 0; Specify whether or not enumerated type arrays (other than std_logic-based); will appear as memories.; The default is 1 (display enumerated type arrays as memories).; ShowEnumMem = 0; Specify whether or not arrays of 3 or more dimensions will appear as memories.; The default is 1 (display 3D+ type arrays as memories).; Show3DMem = 0; Turn on/off undebuggable SystemC type warnings. Default is on.; ShowUndebuggableScTypeWarning = 0; Turn on/off unassociated SystemC name warnings. Default is off.; ShowUnassociatedScNameWarning = 1; Turn on/off PSL assertion pass enable. Default is off.; AssertionPassEnable = 1; Turn on/off PSL assertion fail enable. Default is on.; AssertionFailEnable = 0; Set PSL assertion pass limit. Default is 1.; Any positive integer, -1 for infinity.; AssertionPassLimit = -1; Set PSL assertion fail limit. Default is 1.; Any positive integer, -1 for infinity.; AssertionFailLimit = -1; Turn on/off PSL assertion pass log. Default is on.; AssertionPassLog = 0; Turn on/off PSL assertion fail log. Default is on.; AssertionFailLog = 0; Set action type for PSL assertion fail action. Default is continue.; 0 = Continue 1 = Break 2 = Exit; AssertionFailAction = 1[lmc]; ModelSim's interface to Logic Modeling's SmartModel SWIFT softwarelibsm = $MODEL_TECH/libsm.sl; ModelSim's interface to Logic Modeling's SmartModel SWIFT software (Windows NT); libsm = $MODEL_TECH/libsm.dll; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700); libswift = $LMC_HOME/lib/hp700.lib/libswift.sl; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000); libswift = $LMC_HOME/lib/ibmrs.lib/swift.o; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris); libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so; Logic Modeling's SmartModel SWIFT software (Windows NT); libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll; Logic Modeling's SmartModel SWIFT software (Linux); libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so; ModelSim's interface to Logic Modeling's hardware modeler SFI softwarelibhm = $MODEL_TECH/libhm.sl; ModelSim's interface to Logic Modeling's hardware modeler SFI software (Windows NT); libhm = $MODEL_TECH/libhm.dll; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700); libsfi = <sfi_dir>/lib/hp700/libsfi.sl; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000); libsfi = <sfi_dir>/lib/rs6000/libsfi.a; Logic Modeling's hardware modeler SFI software (Sun4 Solaris); libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so; Logic Modeling's hardware modeler SFI software (Windows NT); libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll; Logic Modeling's hardware modeler SFI software (Linux); libsfi = <sfi_dir>/lib/linux/libsfi.so[Project]Project_Version = 5Project_DefaultLib = workProject_SortMethod = unusedProject_Files_Count = 0Project_Sim_Count = 0Project_Folder_Count = 0Echo_Compile_Output = 0Save_Compile_Report = 1VHDL_DoubleClick = EditVERILOG_DoubleClick = EditSYSTEMC_DoubleClick = EditTCL_DoubleClick = EditTEXT_DoubleClick = EditVHDL_CustomDoubleClick = VERILOG_CustomDoubleClick = SYSTEMC_CustomDoubleClick = TCL_CustomDoubleClick = TEXT_CustomDoubleClick = ForceSoftPaths = 0
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