_primary.vhd

来自「完整的I2C slave model以及spec詳附在內,適合想利用verilo」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity i2c_slave is
    port(
        scl             : in     vl_logic;
        sda_i           : in     vl_logic;
        sda_oe          : in     vl_logic;
        sda_o           : out    vl_logic
    );
end i2c_slave;