top.v

完整的I2C slave model以及spec詳附在內,適合想利用verilog開發此類傳輸的人參考

`timescale 1us/10ps
`define clk_period 60
module top;

wire sda_o;
reg scl,sda_i,sda_oe;
reg nrst,clk;
initial begin
      nrst=1; clk=1;sda_oe=1; 
  #80 nrst=0;
  #30 nrst=1;
end

always #(`clk_period/2) clk=~clk;

task idle;
input [2:0] num;
integer i;
begin
  for(i=0;i<=num;i=i+1)
  @(posedge clk);
end
endtask

task Release_bus;
begin
   scl=1;
   sda_i=1;
   sda_oe=1;
end
endtask

task start;
begin
   @(posedge clk);       
   sda_oe=1;
   sda_i=0;
   scl=1;
   
   @(posedge clk);
   scl=0; 
end
endtask

task stop;
begin
   scl=1;
   sda_oe=1;
   @(negedge clk);
   sda_i=1;
   @(posedge clk);
end
endtask

task trans_bit;
input bit;
begin
  scl=0;
  sda_i=0;
  sda_oe=1;
  @(posedge clk);   
  sda_i=bit;
  @(posedge clk);
  scl=1;
  @(posedge clk);
  scl=0;
  @(posedge clk)
  sda_i=0;  
end
endtask

task issue_command;
input rd_wr;
begin
  scl=0;
  sda_i=0;
  sda_oe=1;
  @(posedge clk);   
  sda_i=rd_wr;        // 0: write   1: read
  @(posedge clk);
  scl=1;
  @(posedge clk);
  scl=0;
  @(posedge clk)
  sda_i=0;  
end
endtask

task ack2slave;
begin
  scl=0;
  sda_i=0;
  sda_oe=1;
  @(posedge clk);
  scl=1;   
  @(posedge clk);
  scl=0;
  sda_i=0;
  @(posedge clk);
  @(posedge clk);
end
endtask

task wait_slaves_ack;
begin
  scl=0;
  sda_i=0;
  sda_oe=0;
  @(posedge clk);
  scl=1;   
  @(posedge clk);
  scl=0;
  sda_i=0;
  @(posedge clk);
  @(posedge clk);      
end
endtask

task write_addr;
input [6:0] addr;
integer i;
begin
  @(posedge clk);
  for (i=0;i<=6;i=i+1)
  begin
    trans_bit(addr[6-i]);
    @(negedge clk);
  end  
  @(posedge clk);  
end
endtask

task write_data;
input [7:0] data;
integer i;
begin
  @(posedge clk);
  for (i=0;i<=7;i=i+1)
  begin
    trans_bit(data[7-i]);
    @(negedge clk);
  end  
  @(posedge clk);  
end
endtask

task read_data;
integer i;
begin
  sda_oe=0;
  for (i=0;i<=7;i=i+1)
  begin
    @(negedge clk);  
    @(posedge clk);
      scl=1;   
    @(posedge clk);
      scl=0;   
    @(posedge clk);
    @(posedge clk);              
  end    
  @(negedge clk);
end
endtask

task single_transfer;
input       rd_wr;
input [6:0] addr;
input [7:0] data;
begin
   start;
   write_addr(addr);   
   issue_command(rd_wr);   
   wait_slaves_ack; 
   
  if (~rd_wr) begin 
   write_data(data);   
   wait_slaves_ack;     
  end else begin
   read_data; 
   ack2slave;
  end        
  stop;
end
endtask

task burst_transfer;
input [2:0]  burst;
input        rd_wr;
input [6:0]  start_addr;
input [39:0] data;
integer      i;
reg   [2:0]  indx; 
begin
   indx<=0;
   start;
   write_addr(start_addr);
   issue_command(rd_wr);
   wait_slaves_ack;   
   if (~rd_wr) 
     for (i=0;i<=burst;i=i+1)
     begin
       indx=i;     // 糶Θ index<=i 穦