fujieqiall.map.eqn

用FPGA实现数字复接?肍PGA实现数字复接

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-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
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-- applicable agreement for further details.
--P1_q[4] is shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[4]
--operation mode is up_dn_cntr

P1_q[4]_lut_out = P1_q[4] $ P1L9;
P1_q[4] = DFFEA(P1_q[4]_lut_out, !clk, , , , , );

--P1L21Q is shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[4]~0
--operation mode is up_dn_cntr

P1L21Q = P1_q[4];


--P1_q[3] is shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[3]
--operation mode is up_dn_cntr

P1_q[3]_lut_out = P1_q[3] $ P1L7;
P1_q[3] = DFFEA(P1_q[3]_lut_out, !clk, , , , , );

--P1L19Q is shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[3]~1
--operation mode is up_dn_cntr

P1L19Q = P1_q[3];

--P1L9 is shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT
--operation mode is up_dn_cntr

P1L9 = CARRY(P1_q[3] & (P1L7));


--M1L1 is shixusuccessful:m5|yimaqi:u3|Y0~57
--operation mode is normal

M1L1 = P1_q[4] # P1_q[3];

--M1L5 is shixusuccessful:m5|yimaqi:u3|Y0~61
--operation mode is normal

M1L5 = P1_q[4] # P1_q[3];


--M1L2 is shixusuccessful:m5|yimaqi:u3|Y0~58
--operation mode is normal

M1L2 = P1_q[4] # !P1_q[3];

--M1L6 is shixusuccessful:m5|yimaqi:u3|Y0~62
--operation mode is normal

M1L6 = P1_q[4] # !P1_q[3];


--M1L3 is shixusuccessful:m5|yimaqi:u3|Y0~59
--operation mode is normal

M1L3 = P1_q[3] # !P1_q[4];

--M1L7 is shixusuccessful:m5|yimaqi:u3|Y0~63
--operation mode is normal

M1L7 = P1_q[3] # !P1_q[4];


--M1L4 is shixusuccessful:m5|yimaqi:u3|Y0~60
--operation mode is normal

M1L4 = !P1_q[3] # !P1_q[4];

--M1L8 is shixusuccessful:m5|yimaqi:u3|Y0~64
--operation mode is normal

M1L8 = !P1_q[3] # !P1_q[4];


--P1_q[2] is shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[2]
--operation mode is up_dn_cntr

P1_q[2]_lut_out = P1_q[2] $ P1L5;
P1_q[2] = DFFEA(P1_q[2]_lut_out, !clk, , , , , );

--P1L17Q is shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[2]~2
--operation mode is up_dn_cntr

P1L17Q = P1_q[2];

--P1L7 is shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT
--operation mode is up_dn_cntr

P1L7 = CARRY(P1_q[2] & (P1L5));


--P2_q[0] is count16:m6|lpm_counter:count_4_rtl_1|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is up_dn_cntr

P2_q[0]_lut_out = !P2_q[0];
P2_q[0] = DFFEA(P2_q[0]_lut_out, clk, , , , , );

--P2L9Q is count16:m6|lpm_counter:count_4_rtl_1|alt_counter_f10ke:wysi_counter|q[0]~0
--operation mode is up_dn_cntr

P2L9Q = P2_q[0];

--P2L3 is count16:m6|lpm_counter:count_4_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is up_dn_cntr

P2L3 = CARRY(P2_q[0]);


--P2_q[1] is count16:m6|lpm_counter:count_4_rtl_1|alt_counter_f10ke:wysi_counter|q[1]
--operation mode is up_dn_cntr

P2_q[1]_lut_out = P2_q[1] $ P2L3;
P2_q[1] = DFFEA(P2_q[1]_lut_out, clk, , , , , );

--P2L11Q is count16:m6|lpm_counter:count_4_rtl_1|alt_counter_f10ke:wysi_counter|q[1]~1
--operation mode is up_dn_cntr

P2L11Q = P2_q[1];

--P2L5 is count16:m6|lpm_counter:count_4_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT
--operation mode is up_dn_cntr

P2L5 = CARRY(P2_q[1] & (P2L3));


--H3L1 is neimacs0:m3|mux_8:u1|Y~11
--operation mode is normal

H3L1 = P2_q[0] & (P2_q[1]) # !P2_q[0] & (P2_q[1] & c1 # !P2_q[1] & (c3));

--H3L5 is neimacs0:m3|mux_8:u1|Y~15
--operation mode is normal

H3L5 = P2_q[0] & (P2_q[1]) # !P2_q[0] & (P2_q[1] & c1 # !P2_q[1] & (c3));


--H3L2 is neimacs0:m3|mux_8:u1|Y~12
--operation mode is normal

H3L2 = P2_q[0] & (H3L1 & (c0) # !H3L1 & c2) # !P2_q[0] & (H3L1);

--H3L6 is neimacs0:m3|mux_8:u1|Y~16
--operation mode is normal

H3L6 = P2_q[0] & (H3L1 & (c0) # !H3L1 & c2) # !P2_q[0] & (H3L1);


--H3L3 is neimacs0:m3|mux_8:u1|Y~13
--operation mode is normal

H3L3 = P2_q[1] & (P2_q[0]) # !P2_q[1] & (P2_q[0] & c6 # !P2_q[0] & (c7));

--H3L7 is neimacs0:m3|mux_8:u1|Y~17
--operation mode is normal

H3L7 = P2_q[1] & (P2_q[0]) # !P2_q[1] & (P2_q[0] & c6 # !P2_q[0] & (c7));


--H3L4 is neimacs0:m3|mux_8:u1|Y~14
--operation mode is normal

H3L4 = P2_q[1] & (H3L3 & (c4) # !H3L3 & c5) # !P2_q[1] & (H3L3);

--H3L8 is neimacs0:m3|mux_8:u1|Y~18
--operation mode is normal

H3L8 = P2_q[1] & (H3L3 & (c4) # !H3L3 & c5) # !P2_q[1] & (H3L3);


--P2_q[2] is count16:m6|lpm_counter:count_4_rtl_1|alt_counter_f10ke:wysi_counter|q[2]
--operation mode is up_dn_cntr

P2_q[2]_lut_out = P2_q[2] $ P2L5;
P2_q[2] = DFFEA(P2_q[2]_lut_out, clk, , , , , );

--P2L13Q is count16:m6|lpm_counter:count_4_rtl_1|alt_counter_f10ke:wysi_counter|q[2]~2
--operation mode is up_dn_cntr

P2L13Q = P2_q[2];


--J3L1 is neimacs0:m3|tri_gate0:u2|dout0~14
--operation mode is normal

J3L1 = M1L2 # P2_q[2] & H3L2 # !P2_q[2] & (H3L4);

--J3L2 is neimacs0:m3|tri_gate0:u2|dout0~15
--operation mode is normal

J3L2 = M1L2 # P2_q[2] & H3L2 # !P2_q[2] & (H3L4);


--H1L1 is neimacs0:m1|mux_8:u1|Y~11
--operation mode is normal

H1L1 = P2_q[0] & (P2_q[1]) # !P2_q[0] & (P2_q[1] & a1 # !P2_q[1] & (a3));

--H1L5 is neimacs0:m1|mux_8:u1|Y~15
--operation mode is normal

H1L5 = P2_q[0] & (P2_q[1]) # !P2_q[0] & (P2_q[1] & a1 # !P2_q[1] & (a3));


--H1L2 is neimacs0:m1|mux_8:u1|Y~12
--operation mode is normal

H1L2 = P2_q[0] & (H1L1 & (a0) # !H1L1 & a2) # !P2_q[0] & (H1L1);

--H1L6 is neimacs0:m1|mux_8:u1|Y~16
--operation mode is normal

H1L6 = P2_q[0] & (H1L1 & (a0) # !H1L1 & a2) # !P2_q[0] & (H1L1);


--H1L3 is neimacs0:m1|mux_8:u1|Y~13
--operation mode is normal

H1L3 = P2_q[1] & (P2_q[0]) # !P2_q[1] & (P2_q[0] & a6 # !P2_q[0] & (a7));

--H1L7 is neimacs0:m1|mux_8:u1|Y~17
--operation mode is normal

H1L7 = P2_q[1] & (P2_q[0]) # !P2_q[1] & (P2_q[0] & a6 # !P2_q[0] & (a7));


--H1L4 is neimacs0:m1|mux_8:u1|Y~14
--operation mode is normal

H1L4 = P2_q[1] & (H1L3 & (a4) # !H1L3 & a5) # !P2_q[1] & (H1L3);

--H1L8 is neimacs0:m1|mux_8:u1|Y~18
--operation mode is normal

H1L8 = P2_q[1] & (H1L3 & (a4) # !H1L3 & a5) # !P2_q[1] & (H1L3);


--J1L1 is neimacs0:m1|tri_gate0:u2|dout0~14
--operation mode is normal

J1L1 = M1L4 # P2_q[2] & H1L2 # !P2_q[2] & (H1L4);

--J1L2 is neimacs0:m1|tri_gate0:u2|dout0~15
--operation mode is normal

J1L2 = M1L4 # P2_q[2] & H1L2 # !P2_q[2] & (H1L4);


--H2L1 is neimacs0:m2|mux_8:u1|Y~11
--operation mode is normal

H2L1 = P2_q[0] & (P2_q[1]) # !P2_q[0] & (P2_q[1] & b1 # !P2_q[1] & (b3));

--H2L5 is neimacs0:m2|mux_8:u1|Y~15
--operation mode is normal

H2L5 = P2_q[0] & (P2_q[1]) # !P2_q[0] & (P2_q[1] & b1 # !P2_q[1] & (b3));


--H2L2 is neimacs0:m2|mux_8:u1|Y~12
--operation mode is normal

H2L2 = P2_q[0] & (H2L1 & (b0) # !H2L1 & b2) # !P2_q[0] & (H2L1);

--H2L6 is neimacs0:m2|mux_8:u1|Y~16
--operation mode is normal

H2L6 = P2_q[0] & (H2L1 & (b0) # !H2L1 & b2) # !P2_q[0] & (H2L1);


--H2L3 is neimacs0:m2|mux_8:u1|Y~13
--operation mode is normal

H2L3 = P2_q[1] & (P2_q[0]) # !P2_q[1] & (P2_q[0] & b6 # !P2_q[0] & (b7));

--H2L7 is neimacs0:m2|mux_8:u1|Y~17
--operation mode is normal

H2L7 = P2_q[1] & (P2_q[0]) # !P2_q[1] & (P2_q[0] & b6 # !P2_q[0] & (b7));


--H2L4 is neimacs0:m2|mux_8:u1|Y~14
--operation mode is normal

H2L4 = P2_q[1] & (H2L3 & (b4) # !H2L3 & b5) # !P2_q[1] & (H2L3);

--H2L8 is neimacs0:m2|mux_8:u1|Y~18
--operation mode is normal

H2L8 = P2_q[1] & (H2L3 & (b4) # !H2L3 & b5) # !P2_q[1] & (H2L3);


--J2L1 is neimacs0:m2|tri_gate0:u2|dout0~14
--operation mode is normal

J2L1 = M1L3 # P2_q[2] & H2L2 # !P2_q[2] & (H2L4);

--J2L2 is neimacs0:m2|tri_gate0:u2|dout0~15
--operation mode is normal

J2L2 = M1L3 # P2_q[2] & H2L2 # !P2_q[2] & (H2L4);


--H4L1 is neimacs0:m4|mux_8:u1|Y~11
--operation mode is normal

H4L1 = P2_q[0] & (P2_q[1]) # !P2_q[0] & (P2_q[1] & d1 # !P2_q[1] & (d3));

--H4L5 is neimacs0:m4|mux_8:u1|Y~15
--operation mode is normal

H4L5 = P2_q[0] & (P2_q[1]) # !P2_q[0] & (P2_q[1] & d1 # !P2_q[1] & (d3));


--H4L2 is neimacs0:m4|mux_8:u1|Y~12
--operation mode is normal

H4L2 = P2_q[0] & (H4L1 & (d0) # !H4L1 & d2) # !P2_q[0] & (H4L1);

--H4L6 is neimacs0:m4|mux_8:u1|Y~16
--operation mode is normal

H4L6 = P2_q[0] & (H4L1 & (d0) # !H4L1 & d2) # !P2_q[0] & (H4L1);


--H4L3 is neimacs0:m4|mux_8:u1|Y~13
--operation mode is normal

H4L3 = P2_q[1] & (P2_q[0]) # !P2_q[1] & (P2_q[0] & d6 # !P2_q[0] & (d7));

--H4L7 is neimacs0:m4|mux_8:u1|Y~17
--operation mode is normal

H4L7 = P2_q[1] & (P2_q[0]) # !P2_q[1] & (P2_q[0] & d6 # !P2_q[0] & (d7));


--H4L4 is neimacs0:m4|mux_8:u1|Y~14
--operation mode is normal

H4L4 = P2_q[1] & (H4L3 & (d4) # !H4L3 & d5) # !P2_q[1] & (H4L3);

--H4L8 is neimacs0:m4|mux_8:u1|Y~18
--operation mode is normal

H4L8 = P2_q[1] & (H4L3 & (d4) # !H4L3 & d5) # !P2_q[1] & (H4L3);


--F1L1 is andmen:m11|outp~98
--operation mode is normal

F1L1 = M1L1 # P2_q[2] & H4L2 # !P2_q[2] & (H4L4);

--F1L3 is andmen:m11|outp~100
--operation mode is normal

F1L3 = M1L1 # P2_q[2] & H4L2 # !P2_q[2] & (H4L4);


--F1L2 is andmen:m11|outp~99
--operation mode is normal

F1L2 = J3L1 & J1L1 & J2L1 & F1L1;

--F1L4 is andmen:m11|outp~101
--operation mode is normal

F1L4 = J3L1 & J1L1 & J2L1 & F1L1;


--P1_q[1] is shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[1]
--operation mode is up_dn_cntr

P1_q[1]_lut_out = P1_q[1] $ P1L3;
P1_q[1] = DFFEA(P1_q[1]_lut_out, !clk, , , , , );

--P1L15Q is shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[1]~3
--operation mode is up_dn_cntr

P1L15Q = P1_q[1];

--P1L5 is shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT
--operation mode is up_dn_cntr

P1L5 = CARRY(P1_q[1] & (P1L3));


--P1_q[0] is shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is up_dn_cntr

P1_q[0]_lut_out = !P1_q[0];
P1_q[0] = DFFEA(P1_q[0]_lut_out, !clk, , , , , );

--P1L13Q is shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[0]~4
--operation mode is up_dn_cntr

P1L13Q = P1_q[0];

--P1L3 is shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is up_dn_cntr

P1L3 = CARRY(P1_q[0]);


--G1_sig_save is djhlatch:m12|sig_save
--operation mode is normal

G1_sig_save = ena & F1L2 # !ena & (G1_sig_save);

--G1L2 is djhlatch:m12|sig_save~1
--operation mode is normal

G1L2 = ena & F1L2 # !ena & (G1_sig_save);


--clk is clk
--operation mode is input

clk = INPUT();


--c2 is c2
--operation mode is input

c2 = INPUT();


--c1 is c1
--operation mode is input

c1 = INPUT();


--c3 is c3
--operation mode is input

c3 = INPUT();


--c0 is c0
--operation mode is input

c0 = INPUT();


--c5 is c5
--operation mode is input

c5 = INPUT();


--c6 is c6
--operation mode is input

c6 = INPUT();


--c7 is c7
--operation mode is input

c7 = INPUT();


--c4 is c4
--operation mode is input

c4 = INPUT();


--a2 is a2
--operation mode is input

a2 = INPUT();


--a1 is a1
--operation mode is input

a1 = INPUT();


--a3 is a3
--operation mode is input

a3 = INPUT();


--a0 is a0
--operation mode is input

a0 = INPUT();


--a5 is a5
--operation mode is input

a5 = INPUT();


--a6 is a6
--operation mode is input

a6 = INPUT();


--a7 is a7
--operation mode is input

a7 = INPUT();


--a4 is a4
--operation mode is input

a4 = INPUT();


--b2 is b2
--operation mode is input

b2 = INPUT();


--b1 is b1
--operation mode is input

b1 = INPUT();


--b3 is b3
--operation mode is input

b3 = INPUT();


--b0 is b0
--operation mode is input

b0 = INPUT();


--b5 is b5
--operation mode is input

b5 = INPUT();


--b6 is b6
--operation mode is input

b6 = INPUT();


--b7 is b7
--operation mode is input

b7 = INPUT();


--b4 is b4
--operation mode is input

b4 = INPUT();


--d2 is d2
--operation mode is input

d2 = INPUT();


--d1 is d1
--operation mode is input

d1 = INPUT();


--d3 is d3
--operation mode is input

d3 = INPUT();


--d0 is d0
--operation mode is input

d0 = INPUT();


--d5 is d5
--operation mode is input

d5 = INPUT();


--d6 is d6
--operation mode is input

d6 = INPUT();


--d7 is d7
--operation mode is input

d7 = INPUT();


--d4 is d4
--operation mode is input

d4 = INPUT();


--ena is ena
--operation mode is input

ena = INPUT();


--S3 is S3
--operation mode is output

S3 = OUTPUT(!M1L1);


--S2 is S2
--operation mode is output

S2 = OUTPUT(!M1L2);


--S1 is S1
--operation mode is output

S1 = OUTPUT(!M1L3);


--S0 is S0
--operation mode is output

S0 = OUTPUT(!M1L4);


--fujieout is fujieout
--operation mode is output

fujieout = OUTPUT(G1_sig_save);