fujieqiall.tan.qmsg

用FPGA实现数字复接?肍PGA实现数字复接

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTAN_COMB_LATCH_NODE" "djhlatch:m12\|sig_save " "Warning: Node \"djhlatch:m12\|sig_save\" is a latch" {  } { { "djhlatch.vhd" "" { Text "F:/EDA/fujieqiall/djhlatch.vhd" 12 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "fujieqiall.vhd" "" { Text "F:/EDA/fujieqiall/fujieqiall.vhd" 6 -1 0 } } { "d:/altera/quartus51sp2/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51sp2/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "ena " "Info: Assuming node \"ena\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "fujieqiall.vhd" "" { Text "F:/EDA/fujieqiall/fujieqiall.vhd" 6 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register shixusuccessful:m5\|count32:u2\|lpm_counter:count_5_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] shixusuccessful:m5\|count32:u2\|lpm_counter:count_5_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] 125.0 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 125.0 MHz between source register \"shixusuccessful:m5\|count32:u2\|lpm_counter:count_5_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]\" and destination register \"shixusuccessful:m5\|count32:u2\|lpm_counter:count_5_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "4.0 ns 4.0 ns 8.0 ns " "Info: fmax restricted to Clock High delay (4.0 ns) plus Clock Low delay (4.0 ns) : restricted to 8.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.100 ns + Longest register register " "Info: + Longest register to register delay is 2.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns shixusuccessful:m5\|count32:u2\|lpm_counter:count_5_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 1 REG LC1_B7 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_B7; Fanout = 2; REG Node = 'shixusuccessful:m5\|count32:u2\|lpm_counter:count_5_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "" { shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus51sp2/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 0.900 ns shixusuccessful:m5\|count32:u2\|lpm_counter:count_5_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[0\]~COUT 2 COMB LC1_B7 2 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 0.900 ns; Loc. = LC1_B7; Fanout = 2; COMB Node = 'shixusuccessful:m5\|count32:u2\|lpm_counter:count_5_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[0\]~COUT'" {  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "0.900 ns" { shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[0] shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus51sp2/libraries/megafunctions/alt_counter_f10ke.tdf" 311 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 1.100 ns shixusuccessful:m5\|count32:u2\|lpm_counter:count_5_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[1\]~COUT 3 COMB LC2_B7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.200 ns) = 1.100 ns; Loc. = LC2_B7; Fanout = 2; COMB Node = 'shixusuccessful:m5\|count32:u2\|lpm_counter:count_5_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[1\]~COUT'" {  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "0.200 ns" { shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus51sp2/libraries/megafunctions/alt_counter_f10ke.tdf" 311 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 1.300 ns shixusuccessful:m5\|count32:u2\|lpm_counter:count_5_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[2\]~COUT 4 COMB LC3_B7 3 " "Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 1.300 ns; Loc. = LC3_B7; Fanout = 3; COMB Node = 'shixusuccessful:m5\|count32:u2\|lpm_counter:count_5_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[2\]~COUT'" {  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "0.200 ns" { shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus51sp2/libraries/megafunctions/alt_counter_f10ke.tdf" 311 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 1.500 ns shixusuccessful:m5\|count32:u2\|lpm_counter:count_5_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[3\]~COUT 5 COMB LC4_B7 1 " "Info: 5: + IC(0.000 ns) + CELL(0.200 ns) = 1.500 ns; Loc. = LC4_B7; Fanout = 1; COMB Node = 'shixusuccessful:m5\|count32:u2\|lpm_counter:count_5_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[3\]~COUT'" {  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "0.200 ns" { shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus51sp2/libraries/megafunctions/alt_counter_f10ke.tdf" 311 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 2.100 ns shixusuccessful:m5\|count32:u2\|lpm_counter:count_5_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] 6 REG LC5_B7 5 " "Info: 6: + IC(0.000 ns) + CELL(0.600 ns) = 2.100 ns; Loc. = LC5_B7; Fanout = 5; REG Node = 'shixusuccessful:m5\|count32:u2\|lpm_counter:count_5_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]'" {  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "0.600 ns" { shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus51sp2/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.100 ns ( 100.00 % ) " "Info: Total cell delay = 2.100 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "2.100 ns" { shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[0] shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "2.100 ns" { shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[0] shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.900ns 0.200ns 0.200ns 0.200ns 0.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK PIN_43 11 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 11; CLK Node = 'clk'" {  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "" { clk } "NODE_NAME" } "" } } { "fujieqiall.vhd" "" { Text "F:/EDA/fujieqiall/fujieqiall.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns shixusuccessful:m5\|count32:u2\|lpm_counter:count_5_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] 2 REG LC5_B7 5 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC5_B7; Fanout = 5; REG Node = 'shixusuccessful:m5\|count32:u2\|lpm_counter:count_5_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]'" {  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "2.000 ns" { clk shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus51sp2/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "3.900 ns" { clk shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.900 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK PIN_43 11 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 11; CLK Node = 'clk'" {  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "" { clk } "NODE_NAME" } "" } } { "fujieqiall.vhd" "" { Text "F:/EDA/fujieqiall/fujieqiall.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns shixusuccessful:m5\|count32:u2\|lpm_counter:count_5_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 2 REG LC1_B7 2 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC1_B7; Fanout = 2; REG Node = 'shixusuccessful:m5\|count32:u2\|lpm_counter:count_5_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "2.000 ns" { clk shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus51sp2/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "3.900 ns" { clk shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "3.900 ns" { clk shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } } { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "3.900 ns" { clk shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus51sp2/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus51sp2/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "2.100 ns" { shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[0] shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "2.100 ns" { shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[0] shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.900ns 0.200ns 0.200ns 0.200ns 0.600ns } } } { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "3.900 ns" { clk shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } } { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "3.900 ns" { clk shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "" { shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "" { shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } {  } {  } } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus51sp2/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}