fujieqiall.vhd

用FPGA实现数字复接?肍PGA实现数字复接

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;

entity fujieqiall is
port(clk,ena:in	std_logic;
a0,a1,a2,a3,a4,a5,a6,a7:in	std_logic;
b0,b1,b2,b3,b4,b5,b6,b7:in	std_logic;
c0,c1,c2,c3,c4,c5,c6,c7:in	std_logic;
d0,d1,d2,d3,d4,d5,d6,d7:in	std_logic;
S3,S2,S1,S0:out   std_logic;
fujieout:out   std_logic
);
end fujieqiall ;
architecture behv of fujieqiall is
component count16 is
	port(clk:in	std_logic;
	D,C,B,A:out   std_logic
	);
end component ;

component neimacs0 is
port(in0_8,in0_7,in0_6,in0_5,in0_4,in0_3,in0_2,in0_1:in	std_logic;
K3,K2,K1:in	std_logic;
sx0:in	std_logic;
out0:out   std_logic
);
end component ;

component shixusuccessful is
	port(B:in	std_logic;
	S3,S2,S1,S0:out   std_logic
	);
end component ;

component men is
port(in1:in	std_logic;
out1:out std_logic
);
end component ;

component andmen is
port(in1,in2,in3,in4:in	std_logic;
outp:out   std_logic
);
end component ;

component djhlatch is
	port(D,ena:in	std_logic;
	ql:out   std_logic
	);
end component ;

signal w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w101,w11,w12,w13,w14,w15,w16:std_logic;
begin
m1:neimacs0  port map(a0,a1,a2,a3,a4,a5,a6,a7,w3,w2,w1,w4,w15);
m2:neimacs0  port map(b0,b1,b2,b3,b4,b5,b6,b7,w3,w2,w1,w5,w14);
m3:neimacs0  port map(c0,c1,c2,c3,c4,c5,c6,c7,w3,w2,w1,w6,w13);
m4:neimacs0  port map(d0,d1,d2,d3,d4,d5,d6,d7,w3,w2,w1,w7,w12);

m5:shixusuccessful  port map(clk,w7,w6,w5,w4);
m6:count16  port map(clk,w1,w2,w3);

m7:men  port map(w7,s3);
m8:men  port map(w6,s2);
m9:men  port map(w5,s1);
m10:men  port map(w4,s0);

m11:andmen port map(w12,w13,w14,w15,w16);
m12:djhlatch port map(w16,ena,fujieout);

end behv;