📄 fujieqiall.map.talkback.xml
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<!--
This XML file (created on Mon May 22 23:10:19 2006) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature. To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder. For more information, go
to www.altera.com/products/software/download/dnl-download_license.html
-->
<talkback>
<ver>5.1</ver>
<schema>quartus_version_5.1_build_216.xsd</schema><license>
<nic_id>000c76594cd8</nic_id>
<cdrive_id>7886784f</cdrive_id>
</license>
<tool>
<name>Quartus II</name>
<version>5.1</version>
<build>Build 216</build>
<service_pack_label>2</service_pack_label>
<binary_type>32</binary_type>
<module>quartus_map.exe</module>
<edition>Web Edition</edition>
<eval>Eval</eval>
<compilation_end_time>Mon May 22 23:10:20 2006</compilation_end_time>
</tool>
<machine>
<os>Windows XP</os>
<cpu>
<proc_count>1</proc_count>
<cpu_freq units="MHz">2019</cpu_freq>
</cpu>
<ram units="MB">224</ram>
</machine>
<top_file>F:/EDA/fujieqiall/fujieqiall</top_file>
<compilation_summary>
<flow_status>Successful - Mon May 22 23:10:19 2006</flow_status>
<quartus_ii_version>5.1 Build 216 03/06/2006 SP 2 SJ Web Edition</quartus_ii_version>
<revision_name>fujieqiall</revision_name>
<top_level_entity_name>fujieqiall</top_level_entity_name>
<family>FLEX10K</family>
<met_timing_requirements>N/A</met_timing_requirements>
<total_logic_elements>34</total_logic_elements>
<total_pins>39</total_pins>
<total_memory_bits>0</total_memory_bits>
</compilation_summary>
<compile_id>FE62B8A2</compile_id>
<mep_data>
<command_line>quartus_map --read_settings_files=on --write_settings_files=off fujieqiall -c fujieqiall</command_line>
</mep_data>
<software_data>
<smart_recompile>off</smart_recompile>
</software_data>
<messages>
<warning>Warning (10631): VHDL Process Statement warning at djhlatch.vhd(12): signal or variable "sig_save" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "sig_save" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.</warning>
<warning>Warning (10492): VHDL Process Statement warning at djhlatch.vhd(17): signal "sig_save" is read inside the Process Statement but isn't in the Process Statement's sensivitity list</warning>
<warning>Warning (10492): VHDL Process Statement warning at mux_8.vhd(24): signal "D7" is read inside the Process Statement but isn't in the Process Statement's sensivitity list</warning>
<warning>Warning (10492): VHDL Process Statement warning at mux_8.vhd(23): signal "D6" is read inside the Process Statement but isn't in the Process Statement's sensivitity list</warning>
<warning>Warning (10492): VHDL Process Statement warning at mux_8.vhd(22): signal "D5" is read inside the Process Statement but isn't in the Process Statement's sensivitity list</warning>
<info>Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings</info>
<info>Info: Elapsed time: 00:00:17</info>
<info>Info: Processing ended: Mon May 22 23:10:18 2006</info>
<info>Info: Implemented 73 device resources after synthesis - the final resource count might be different</info>
<info>Info: Implemented 34 logic cells</info>
</messages>
<analysis___synthesis_settings>
<row>
<option>Top-level entity name</option>
<setting>fujieqiall</setting>
<default_value>fujieqiall</default_value>
</row>
<row>
<option>Family name</option>
<setting>FLEX10K</setting>
<default_value>Stratix</default_value>
</row>
<row>
<option>Use smart compilation</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Create Debugging Nodes for IP Cores</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Preserve fewer node names</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Disable OpenCore Plus hardware evaluation</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Verilog Version</option>
<setting>Verilog_2001</setting>
<default_value>Verilog_2001</default_value>
</row>
<row>
<option>VHDL Version</option>
<setting>VHDL93</setting>
<default_value>VHDL93</default_value>
</row>
<row>
<option>State Machine Processing</option>
<setting>Auto</setting>
<default_value>Auto</default_value>
</row>
<row>
<option>Extract Verilog State Machines</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Extract VHDL State Machines</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Add Pass-Through Logic to Inferred RAMs</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>NOT Gate Push-Back</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Power-Up Don't Care</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Remove Redundant Logic Cells</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Remove Duplicate Registers</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Ignore CARRY Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore CASCADE Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore GLOBAL Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore ROW GLOBAL Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore LCELL Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore SOFT Buffers</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Limit AHDL Integers to 32 Bits</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Auto Implement in ROM</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Optimization Technique -- FLEX 10K/10KE/10KA/ACEX 1K</option>
<setting>Area</setting>
<default_value>Area</default_value>
</row>
<row>
<option>Carry Chain Length -- FLEX 10K</option>
<setting>32</setting>
<default_value>32</default_value>
</row>
<row>
<option>Cascade Chain Length</option>
<setting>2</setting>
<default_value>2</default_value>
</row>
<row>
<option>Auto Carry Chains</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto Open-Drain Pins</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Remove Duplicate Logic</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto ROM Replacement</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto RAM Replacement</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto Clock Enable Replacement</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto Resource Sharing</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Allow Any RAM Size For Recognition</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Allow Any ROM Size For Recognition</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore translate_off and translate_on Synthesis Directives</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Show Parameter Settings Tables in Synthesis Report</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>HDL message level</option>
<setting>Level2</setting>
<default_value>Level2</default_value>
</row>
</analysis___synthesis_settings>
<general_register_statistics>
<row>
<statistic>Total registers</statistic>
<value>8</value>
</row>
<row>
<statistic>Number of registers using Synchronous Clear</statistic>
<value>0</value>
</row>
<row>
<statistic>Number of registers using Synchronous Load</statistic>
<value>0</value>
</row>
<row>
<statistic>Number of registers using Asynchronous Clear</statistic>
<value>0</value>
</row>
<row>
<statistic>Number of registers using Asynchronous Load</statistic>
<value>0</value>
</row>
<row>
<statistic>Number of registers using Clock Enable</statistic>
<value>0</value>
</row>
<row>
<statistic>Number of registers using Preset</statistic>
<value>0</value>
</row>
</general_register_statistics>
</talkback>
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