__projnav.log

一个在xilinx公司ise编译环境下仿真成功的键盘操作程序。

ISE Auto-Make Log File
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Starting: 'jhdparse @_key1.jp'


JHDPARSE - VHDL/Verilog Parser.
ISE 4.1i Copyright(c) 1999-2001 Xilinx, Inc.  All rights reserved. 

Scanning    d:/xilinx_webpack/data/simprim.lst
Scanning    d:/xilinx_webpack/verilog/src/iSE/unisim_comp.v
Scanning    key1.v
Writing key1.jhd.

JHDPARSE complete -    0 errors,    0 warnings.

Done: completed successfully.

ISE Auto-Make Log File
-----------------------

Starting: 'exewrap @__filesAllClean_exewrap.rsp'


Creating TCL Process
Cleaning Up Project
deleting file(s): __projnav.log _map.log _par.log _impact.log
deleting file(s): automake.err
deleting file(s): keyled.nc1
deleting file(s): keyled_map.ncd keyled.ncd
deleting file(s): keyled.ngd
deleting file(s): keyled.ngm
deleting file(s): __impact.rsp __keyled_2prj_exewrap.rsp __ednTOngd_exewrap.rsp __ngdbuild.rsp _map.rsp _ngdTOnc1_exewrap.rsp _par.rsp _prepar.rsp _nc1TOncd_exewrap.rsp bitgen.rsp __filesAllClean_exewrap.rsp
deleting file(s): keyled.syr
deleting file(s): keyled._prj
deleting file(s): keyled.bld
deleting file(s): keyled.mrp
deleting file(s): keyled.par
deleting file(s): keyled.pad
deleting file(s): keyled.dly
deleting file(s): keyled.ut bitgen.ut
deleting file(s): keyled.bit
deleting file(s): keyled.bgn
deleting file(s): keyled.drc
deleting file(s): par.opt
deleting file(s): keyled.xpi
deleting file(s): keyled.pcf
deleting file(s): keyled_ngdbuild.nav
deleting directory: _ngo
Finished cleaning up project

Done: completed successfully.

ISE Auto-Make Log File
-----------------------

Updating: Edit Implementation Constraints File

Starting: 'exewrap @_editucf_exewrap.rsp'


Creating TCL Process
copy Foundation UCF template
Starting: 'notepad key1.ucf'


Tcl d:/xilinx_webpack/data/projnav/_editucf.tcl detected that program 'notepad key1.ucf' completed successfully.

Starting: 'chkdate'


Tcl d:/xilinx_webpack/data/projnav/_editucf.tcl detected that program 'chkdate' completed successfully.

 Implementation Results have been RESET!
 Please re-run the 'Implement Design' process so that your constraint changes are incorporated.
Done: completed successfully.

ISE Auto-Make Log File
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Updating: Configure Device (iMPACT)

Starting: 'exewrap @__key1_2prj_exewrap.rsp'


Creating TCL Process
Done: completed successfully.

Starting: 'exewrap -mode pipe -tapkeep -command D:/xilinx_webpack/bin/nt/xst.exe -ifn key1.xst -ofn key1.syr'


Starting: 'D:/xilinx_webpack/bin/nt/xst.exe -ifn key1.xst -ofn key1.syr '


Release 4.1WP3.x - xst E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to .
CPU : 0.00 / 0.11 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter overwrite set to YES
CPU : 0.06 / 0.17 s | Elapsed : 0.00 / 0.00 s
 
--> =========================================================================
---- Source Parameters
Input Format                       : VERILOG
Input File Name                    : key1.prj

---- Target Parameters
Target Device                      : xc2s100-pq208-5
Output File Name                   : key1
Output Format                      : NGC
Target Technology                  : spartan2

---- Source Options
Top Module Name                    : key1
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Flip-Flop Type                 : D
Mux Extraction                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES
ROM Extraction                     : Yes
RAM Extraction                     : Yes
RAM Style                          : Auto
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
Add Generic Clock Buffer(BUFG)     : 4
Global Maximum Fanout              : 100
Register Duplication               : YES
Move First FlipFlop Stage          : YES
Move Last FlipFlop Stage           : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Speed Grade                        : 5

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Check Attribute Syntax             : YES
Keep Hierarchy                     : No
Global Optimization                : AllClockNets
Write Timing Constraints           : No
Incremental Synthesis              : NO

=========================================================================

 
Compiling source file : key1.prj
Compiling included source file 'key1.v'
Module <key1> compiled.
Continuing compilation of source file 'key1.prj'
Compiling included source file 'd:/xilinx_webpack/verilog/src/iSE/unisim_comp.v'
Continuing compilation of source file 'key1.prj'
No errors in compilation
Analysis of file <key1.prj> succeeded.
 
 
Starting Verilog synthesis.
 
Analyzing top module <key1>.
Module <key1> is correct for synthesis.

Synthesizing Unit <key1>.
    Related source file is key1.v.
Unit <key1> synthesized.

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================


Starting low level synthesis...
Optimizing unit <key1> ...

Building and optimizing final netlist ...

=========================================================================
Final Results
Top Level Output File Name         : key1
Output Format                      : NGC
Optimization Criterion             : Speed
Target Technology                  : spartan2
Keep Hierarchy                     : No
Macro Generator                    : macro+

Design Statistics
# IOs                              : 16

Cell Usage :
# IO Buffers                       : 16
#      IBUF                        : 8
#      OBUF                        : 8
=========================================================================


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 7.631ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               7.631ns (Levels of Logic = 2)
  Source:            keyin_7
  Destination:       ledout_7

  Data Path: keyin_7 to ledout_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    IBUF:I->O              1   0.924   1.150  keyin_7_IBUF (ledout_7_OBUF)
    OBUF:I->O                  5.557          ledout_7_OBUF (ledout_7)
    ----------------------------------------
    Total                      7.631ns (6.481ns logic, 1.150ns route)
                                       (84.9% logic, 15.1% route)

=========================================================================
CPU : 1.15 / 1.32 s | Elapsed : 1.00 / 1.00 s
 
--> 
EXEWRAP detected that program 'D:/xilinx_webpack/bin/nt/xst.exe' completed successfully.

Done: completed successfully.

Starting: 'exewrap @__ednTOngd_exewrap.rsp'


Starting: 'ngdbuild -f __ngdbuild.rsp '


Release 4.1WP3.x - ngdbuild E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -dd f:/dp_fpga/dp-fpga/xc2s100/key/_ngo -nt timestamp -p
xc2s100-pq208-5 key1.ngc key1.ngd 

Reading NGO file "F:/dp_fpga/dp-fpga/xc2s100/key/key1.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "key1.ucf" ...

Checking timing specifications ...

Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "key1.ngd" ...

Writing NGDBUILD log file "key1.bld"...

NGDBUILD done.
EXEWRAP detected that program 'ngdbuild' completed successfully.

Done: completed successfully.

Starting: 'exewrap @_ngdTOnc1_exewrap.rsp'


Creating TCL Process
Starting: 'map -f _map.rsp'


Release 4.1WP3.x - Map E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
Using target part "2s100pq208-5".
Removing unused or disabled logic...
Running cover...
Writing file key1.ngm...
Running directed packing...
Running delay-based packing...
Running related packing...
Writing design file "key1.ncd"...

Design Summary:
   Number of errors:      0
   Number of warnings:    0
   Number of Slices:                  0 out of  1,200    0%
   Number of Slices containing
      unrelated logic:                0 out of      0    0%
   Number of 4 input LUTs:            0 out of  2,400    0%
   Number of bonded IOBs:            16 out of    140   11%
Total equivalent gate count for design:  0
Additional JTAG gate count for IOBs:  768

Mapping completed.
See MAP report file "key1.mrp" for details.
Tcl d:/xilinx_webpack/data/projnav/_map.tcl detected that program 'map -f _map.rsp' completed successfully.

Done: completed successfully.

Starting: 'exewrap @_nc1TOncd_exewrap.rsp'


Creating TCL Process
Found _prepar.rsp
Starting: 'par -f _par.rsp'


Release 4.1WP3.x - Par E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.


WARNING:Par:69 - Option "-xe" overrides some effects of "-ol".


Constraints file: key1.pcf

Loading design for application par from file par_temp.ncd.
   "key1" is an NCD, version 2.36, device xc2s100, package pq208, speed -5
Loading device for application par from file 'v100.nph' in environment
D:/xilinx_webpack.
Device speed data version:  PRELIMINARY 1.22 2001-06-20.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External IOBs            16 out of 140    11%
      Number of LOCed External IOBs   16 out of 16    100%





Overall effort level (-ol):   2 (set by user)
Placer effort level (-pl):    2 (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    2 (set by user)
Extra effort level (-xe):     0 (set by user)

Starting the placer. REAL time: 0 secs 
Placement pass 1 .
Placer score = 1065
Placement pass 2 .
Placer score = 1065
Optimizing ... 
Placer score = 1065
All IOBs have been constrained to specific sites.
Placer completed in real time: 0 secs 

Dumping design to file key1.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 1 secs 

0 connection(s) routed; 8 unrouted.
Starting router resource preassignment
Completed router resource preassignment. REAL time: 0 secs 
Starting iterative routing. 
Routing active signals.
.
End of iteration 1 
8 successful; 0 unrouted; (0) REAL time: 2 secs 
Constraints are met. 
Total REAL time: 2 secs 
Total CPU  time: 2 secs 
End of route.  8 routed (100.00%); 0 unrouted.
No errors found. 
Completely routed. 

This design was run without timing constraints.  It is likely that much better
circuit performance can be obtained by trying either or both of the following:

  - Enabling the Delay Based Cleanup router pass, if not already enabled
  - Supplying timing constraints in the input design


Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 2 secs 

Generating PAR statistics.
Dumping design to file key1.ncd.


All signals are completely routed.

Total REAL time to PAR completion: 2 secs 
Total CPU time to PAR completion: 2 secs 

Placement: Completed - No errors found.
Routing: Completed - No errors found.

PAR done.
Tcl d:/xilinx_webpack/data/projnav/_par.tcl detected that program 'par -f _par.rsp' completed successfully.

PAR completed successfully
Done: completed successfully.

Starting: 'exewrap -tcl -command d:/xilinx_webpack/data/projnav/_bitgen.tcl bitgen.rsp key1'


Done: completed successfully.

Starting: 'exewrap -tapkeep -tcl -command d:/xilinx_webpack/data/projnav/_utTObit.tcl key1'


Creating TCL Process
Starting: 'bitgen -f key1.ut key1.ncd'


Release 4.1WP3.x - Bitgen E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.

Loading design for application Bitgen from file key1.ncd.
   "key1" is an NCD, version 2.36, device xc2s100, package pq208, speed -5
Loading device for application Bitgen from file 'v100.nph' in environment
D:/xilinx_webpack.
Opened constraints file key1.pcf.

Mon Feb 17 16:03:39 2003

Running DRC.
DRC detected 0 errors and 0 warnings.
Creating bit map...
Saving bit stream in "key1.bit".
Bitstream generation is complete.
Tcl d:/xilinx_webpack/data/projnav/_utTObit.tcl detected that program 'bitgen -f key1.ut key1.ncd' completed successfully.


Done: completed successfully.

Launching: 'D:\xilinx_webpack\bin\nt\impact.exe -f __impact.rsp'



ISE Auto-Make Log File
-----------------------

Starting: 'jhdparse @_key2.jp'


JHDPARSE - VHDL/Verilog Parser.
ISE 4.1i Copyright(c) 1999-2001 Xilinx, Inc.  All rights reserved.