key2.par

一个在xilinx公司ise编译环境下仿真成功的键盘操作程序。

Release 4.1WP3.x - Par E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.


Mon Feb 17 16:04:59 2003

par -f _par.rsp


Constraints file: key2.pcf

Loading design for application par from file par_temp.ncd.
   "key2" is an NCD, version 2.36, device xc2s100, package pq208, speed -5
Loading device for application par from file 'v100.nph' in environment
D:/xilinx_webpack.
Device speed data version:  PRELIMINARY 1.22 2001-06-20.


Resolved that IOB <ledout<3>> must be placed at site P47.
Resolved that IOB <ledout<4>> must be placed at site P46.
Resolved that IOB <ledout<5>> must be placed at site P45.
Resolved that IOB <ledout<6>> must be placed at site P44.
Resolved that IOB <ledout<7>> must be placed at site P43.
Resolved that IOB <keyin<0>> must be placed at site P62.
Resolved that IOB <keyin<1>> must be placed at site P63.
Resolved that IOB <keyin<2>> must be placed at site P67.
Resolved that IOB <keyin<3>> must be placed at site P68.
Resolved that IOB <keyin<4>> must be placed at site P58.
Resolved that IOB <keyin<5>> must be placed at site P59.
Resolved that IOB <keyin<6>> must be placed at site P60.
Resolved that IOB <keyin<7>> must be placed at site P61.
Resolved that IOB <ledout<0>> must be placed at site P57.
Resolved that IOB <ledout<1>> must be placed at site P49.
Resolved that IOB <ledout<2>> must be placed at site P48.


Device utilization summary:

   Number of External IOBs            16 out of 140    11%
      Number of LOCed External IOBs   16 out of 16    100%

   Number of SLICEs                   11 out of 1200    1%




Overall effort level (-ol):   2 (set by user)
Placer effort level (-pl):    2 (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    2 (set by user)
Extra effort level (-xe):     0 (set by user)

Starting the placer. REAL time: 2 secs 
Placement pass 1 ..
Placer score = 2010
Placement pass 2 ..
Placer score = 2085
Optimizing ... 
Placer score = 1425
All IOBs have been constrained to specific sites.
Placer completed in real time: 2 secs 

Dumping design to file key2.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 1 secs 

0 connection(s) routed; 79 unrouted.
Starting router resource preassignment
Completed router resource preassignment. REAL time: 2 secs 
Starting iterative routing. 
Routing active signals.
....
End of iteration 1 
79 successful; 0 unrouted; (0) REAL time: 3 secs 
Constraints are met. 
Total REAL time: 3 secs 
Total CPU  time: 2 secs 
End of route.  79 routed (100.00%); 0 unrouted.
No errors found. 
Completely routed. 

This design was run without timing constraints.  It is likely that much better
circuit performance can be obtained by trying either or both of the following:

  - Enabling the Delay Based Cleanup router pass, if not already enabled
  - Supplying timing constraints in the input design


Total REAL time to Router completion: 3 secs 
Total CPU time to Router completion: 2 secs 

Generating PAR statistics.

   The Delay Summary Report

   The Score for this design is: 156


The Number of signals not completely routed for this design is: 0

   The Average Connection Delay for this design is:        1.224 ns
   The Maximum Pin Delay is:                               2.021 ns
   The Average Connection Delay on the 10 Worst Nets is:   1.695 ns

   Listing Pin Delays by value: (ns)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
          22          55           2           0           0           0

Dumping design to file key2.ncd.


All signals are completely routed.

Total REAL time to PAR completion: 3 secs 
Total CPU time to PAR completion: 2 secs 

Placement: Completed - No errors found.
Routing: Completed - No errors found.

PAR done.