pwm.syr

一个在xilinx的ise环境下编译仿真成功的pWM程序。

#      1-bit register              : 1
#      10-bit register             : 1
#      21-bit register             : 1
# Adders/Subtractors               : 2
#      10-bit addsub               : 1
#      21-bit adder                : 1
# Comparators                      : 1
#      10-bit comparator less      : 1

Cell Usage :
# BELS                             : 98
#      GND                         : 1
#      LUT1_D                      : 1
#      LUT1_L                      : 15
#      LUT2                        : 11
#      LUT2_L                      : 10
#      MUXCY                       : 34
#      VCC                         : 1
#      XORCY                       : 25
# FlipFlops/Latches                : 27
#      FD                          : 16
#      FDE                         : 10
#      FDR                         : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 3
#      IBUF                        : 2
#      OBUF                        : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s100pq208-5 

 Number of Slices:                      29  out of   1200     2%  
 Number of Slice Flip Flops:            27  out of   2400     1%  
 Number of 4 input LUTs:                37  out of   2400     1%  
 Number of bonded IOBs:                  3  out of    144     2%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clock                              | BUFGP                  | 17    |
count_15:Q                         | NONE                   | 10    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 9.789ns (Maximum Frequency: 102.155MHz)
   Minimum input arrival time before clock: 7.063ns
   Maximum output required time after clock: 7.999ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clock'
Delay:               9.789ns (Levels of Logic = 19)
  Source:            count_0 (FF)
  Destination:       pwm_reg (FF)
  Source Clock:      clock rising
  Destination Clock: clock rising

  Data Path: count_0 to pwm_reg
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               1   1.292   1.150  count_0 (count_0)
     LUT1_D:I0->LO         1   0.653   0.000  pwm__old_count_1<0>lut (N597)
     MUXCY:S->O            1   0.784   0.000  pwm__old_count_1<0>cy (pwm__old_count_1<0>_cyo)
     MUXCY:CI->O           1   0.050   0.000  pwm__old_count_1<1>cy (pwm__old_count_1<1>_cyo)
     MUXCY:CI->O           1   0.050   0.000  pwm__old_count_1<2>cy (pwm__old_count_1<2>_cyo)
     MUXCY:CI->O           1   0.050   0.000  pwm__old_count_1<3>cy (pwm__old_count_1<3>_cyo)
     MUXCY:CI->O           1   0.050   0.000  pwm__old_count_1<4>cy (pwm__old_count_1<4>_cyo)
     MUXCY:CI->O           1   0.050   0.000  pwm__old_count_1<5>cy (pwm__old_count_1<5>_cyo)
     MUXCY:CI->O           1   0.050   0.000  pwm__old_count_1<6>cy (pwm__old_count_1<6>_cyo)
     MUXCY:CI->O           1   0.050   0.000  pwm__old_count_1<7>cy (pwm__old_count_1<7>_cyo)
     MUXCY:CI->O           1   0.050   0.000  pwm__old_count_1<8>cy (pwm__old_count_1<8>_cyo)
     MUXCY:CI->O           1   0.050   0.000  pwm__old_count_1<9>cy (pwm__old_count_1<9>_cyo)
     MUXCY:CI->O           1   0.050   0.000  pwm__old_count_1<10>cy (pwm__old_count_1<10>_cyo)
     MUXCY:CI->O           1   0.050   0.000  pwm__old_count_1<11>cy (pwm__old_count_1<11>_cyo)
     MUXCY:CI->O           1   0.050   0.000  pwm__old_count_1<12>cy (pwm__old_count_1<12>_cyo)
     MUXCY:CI->O           1   0.050   0.000  pwm__old_count_1<13>cy (pwm__old_count_1<13>_cyo)
     MUXCY:CI->O           0   0.050   0.000  pwm__old_count_1<14>cy (pwm__old_count_1<14>_cyo)
     XORCY:CI->O           2   0.500   1.340  pwm__old_count_1<15>_xor (_old_count_1<15>)
     LUT2_L:I0->LO         1   0.653   0.000  XNor_stagelut9 (N319)
     MUXCY:S->O            1   0.784   1.150  XNor_stagecy_rn_8 (XNor_stage_cyo9)
     FDR:R                     0.783          pwm_reg
    ----------------------------------------
    Total                      9.789ns (6.149ns logic, 3.640ns route)
                                       (62.8% logic, 37.2% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'count_15:Q'
Delay:               5.722ns (Levels of Logic = 11)
  Source:            pwm_count_0 (FF)
  Destination:       pwm_count_9 (FF)
  Source Clock:      count_15:Q rising
  Destination Clock: count_15:Q rising

  Data Path: pwm_count_0 to pwm_count_9
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   1.292   1.340  pwm_count_0 (pwm_count_0)
     LUT2:I0->O            1   0.653   0.000  pwm_count_LPM_COUNTER_1__n0000<0>lut (pwm_count_N329)
     MUXCY:S->O            1   0.784   0.000  pwm_count_LPM_COUNTER_1__n0000<0>cy (pwm_count_LPM_COUNTER_1__n0000<0>_cyo)
     MUXCY:CI->O           1   0.050   0.000  pwm_count_LPM_COUNTER_1__n0000<1>cy (pwm_count_LPM_COUNTER_1__n0000<1>_cyo)
     MUXCY:CI->O           1   0.050   0.000  pwm_count_LPM_COUNTER_1__n0000<2>cy (pwm_count_LPM_COUNTER_1__n0000<2>_cyo)
     MUXCY:CI->O           1   0.050   0.000  pwm_count_LPM_COUNTER_1__n0000<3>cy (pwm_count_LPM_COUNTER_1__n0000<3>_cyo)
     MUXCY:CI->O           1   0.050   0.000  pwm_count_LPM_COUNTER_1__n0000<4>cy (pwm_count_LPM_COUNTER_1__n0000<4>_cyo)
     MUXCY:CI->O           1   0.050   0.000  pwm_count_LPM_COUNTER_1__n0000<5>cy (pwm_count_LPM_COUNTER_1__n0000<5>_cyo)
     MUXCY:CI->O           1   0.050   0.000  pwm_count_LPM_COUNTER_1__n0000<6>cy (pwm_count_LPM_COUNTER_1__n0000<6>_cyo)
     MUXCY:CI->O           1   0.050   0.000  pwm_count_LPM_COUNTER_1__n0000<7>cy (pwm_count_LPM_COUNTER_1__n0000<7>_cyo)
     MUXCY:CI->O           0   0.050   0.000  pwm_count_LPM_COUNTER_1__n0000<8>cy (pwm_count_LPM_COUNTER_1__n0000<8>_cyo)
     XORCY:CI->O           1   0.500   0.000  pwm_count_LPM_COUNTER_1__n0000<9>_xor (pwm_count__n0000<9>)
     FDE:D                     0.753          pwm_count_9
    ----------------------------------------
    Total                      5.722ns (4.382ns logic, 1.340ns route)
                                       (76.6% logic, 23.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'count_15:Q'
Offset:              7.063ns (Levels of Logic = 2)
  Source:            keyin<0> (PAD)
  Destination:       pwm_count_9 (FF)
  Destination Clock: count_15:Q rising

  Data Path: keyin<0> to pwm_count_9
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            12   0.924   2.400  keyin_0_IBUF (keyin_0_IBUF)
     LUT2:I1->O           10   0.653   2.200  pwm_count_ClkEn_INV1 (pwm_count_0_N86)
     FDE:CE                    0.886          pwm_count_0
    ----------------------------------------
    Total                      7.063ns (2.463ns logic, 4.600ns route)
                                       (34.9% logic, 65.1% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clock'
Offset:              7.999ns (Levels of Logic = 1)
  Source:            pwm_reg (FF)
  Destination:       pwm_out (PAD)
  Source Clock:      clock rising

  Data Path: pwm_reg to pwm_out
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   1.292   1.150  pwm_reg (pwm_reg)
     OBUF:I->O                 5.557          pwm_out_OBUF (pwm_out)
    ----------------------------------------
    Total                      7.999ns (6.849ns logic, 1.150ns route)
                                       (85.6% logic, 14.4% route)

=========================================================================
CPU : 1.84 / 2.80 s | Elapsed : 2.00 / 3.00 s
 
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Total memory usage is 57348 kilobytes