coregen.log

来自「一个在xilinx的ise环境下编译仿真成功的pWM程序。」· LOG 代码 · 共 23 行

# Xilinx CORE Generator 6.3i
# User = user
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in D:\fpga\xilins2board\Example\pwm\coregen.log
# lockprojectprops=false
# busformat=BusFormatAngleBracketNotRipped
# designflow=VHDL
# expandedprojectpath=D:\fpga\xilins2board\Example\pwm
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=Verilog VHDL
# xilinxfamily=Virtex4
# outputoption=OutputProducts
# overwritefiles=Default
# simvendor=ModelSim
# expandedprojectpath=D:\fpga\xilins2board\Example\pwm
SETPROJECT .
Set current Project to D:\fpga\xilins2board\Example\pwm
SET BusFormat = BusFormatAngleBracketNotRipped
SETXIPCPORTHOST 2379
XIPCPJSENDCORES spartan3