__projnav.log

一个在xilinx的ise环境下编译仿真成功的pWM程序。

Total Number 4 input LUTs:           37 out of  2,400    1%
      Number used as logic:                        22
      Number used as a route-thru:                 15
   Number of bonded IOBs:             3 out of    140    2%
      IOB Flip Flops:                               1
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  525
Additional JTAG gate count for IOBs:  192
Peak Memory Usage:  60 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "pwm_map.mrp" for details.
Completed process "Map".

Mapping Module pwm . . .
MAP command line:
map -intstyle ise -p xc2s100-pq208-5 -cm area -pr b -k 4 -c 100 -tx off -o pwm_map.ncd pwm.ngd pwm.pcf
Mapping Module pwm: DONE



Started process "Place & Route".





Constraints file: pwm.pcf

Loading device database for application Par from file "pwm_map.ncd".
   "pwm" is an NCD, version 2.38, device xc2s100, package pq208, speed -5
Loading device for application Par from file 'v100.nph' in environment
C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2004-06-25.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs             3 out of 140     2%
      Number of LOCed External IOBs    3 out of 3     100%

   Number of SLICEs                   19 out of 1200    1%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9896b5) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.
Phase 5.8 (Checksum:98c979) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file pwm.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 97 unrouted;       REAL time: 0 secs 

Phase 2: 84 unrouted;       REAL time: 0 secs 

Phase 3: 2 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|       clock_BUFGP          |  Global  |    9   |  0.160     |  0.673      |
+----------------------------+----------+--------+------------+-------------+
|         count<15>          |   Local  |    6   |  0.165     |  3.382      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 0 secs 
Total CPU time to PAR completion: 0 secs 

Peak Memory Usage:  49 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file pwm.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Sat Apr 22 20:46:28 2006
--------------------------------------------------------------------------------

Generating Report ...

Error: TRACE failed
Reason: 
Process "Generate Post-Place & Route Static Timing" did not complete.

Place & Route Module pwm . . .
PAR command line: par -w -intstyle ise -ol std -t 1 pwm_map.ncd pwm.ncd pwm.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------



Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "pwm.v"
Module <pwm> compiled
No errors in compilation
Analysis of file <pwm.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <pwm>.
Module <pwm> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <pwm>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <pwm>.
    Related source file is pwm.v.
    Found 10-bit comparator less for signal <$n0003> created at line 13.
    Found 21-bit adder for signal <$old_count_1>.
    Found 21-bit register for signal <count>.
    Found 10-bit updown counter for signal <pwm_count>.
    Found 1-bit register for signal <pwm_reg>.
    Summary:
	inferred   1 Counter(s).
	inferred  22 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <pwm> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 21-bit adder                      : 1
# Counters                         : 1
 10-bit updown counter             : 1
# Registers                        : 2
 21-bit register                   : 1
 1-bit register                    : 1
# Comparators                      : 1
 10-bit comparator less            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <count_20> is unconnected in block <pwm>.

Optimizing unit <pwm> ...
Loading device for application Xst from file 'v100.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block pwm, actual ratio is 2.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s100pq208-5 

 Number of Slices:                      31  out of   1200     2%  
 Number of Slice Flip Flops:            31  out of   2400     1%  
 Number of 4 input LUTs:                41  out of   2400     1%  
 Number of bonded IOBs:                  3  out of    144     2%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clock                              | BUFGP                  | 21    |
count_19:Q                         | NONE                   | 10    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 9.789ns (Maximum Frequency: 102.155MHz)
   Minimum input arrival time before clock: 7.063ns
   Maximum output required time after clock: 7.999ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\fpga\xilins2board\example\pwm/_ngo
-uc pwm.ucf -p xc2s100-pq208-5 pwm.ngc pwm.ngd 

Reading NGO file "D:/fpga/xilins2board/Example/pwm/pwm.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "pwm.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 41448 kilobytes

Writing NGD file "pwm.ngd" ...

Writing NGDBUILD log file "pwm.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s100pq208-5".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        30 out of  2,400    1%
  Number of 4 input LUTs:            22 out of  2,400    1%
Logic Distribution:
    Number of occupied Slices:                          21 out of  1,200    1%
    Number of Slices containing only related logic:     21 out of     21  100%
    Number of Slices containing unrelated logic:         0 out of     21    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:           41 out of  2,400    1%
      Number used as logic:                        22
      Number used as a route-thru:                 19
   Number of bonded IOBs:             3 out of    140    2%
      IOB Flip Flops:                               1
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  581
Additional JTAG gate count for IOBs:  192
Peak Memory Usage:  60 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "pwm_map.mrp" for details.
Completed process "Map".

Mapping Module pwm . . .
MAP command line:
map -intstyle ise -p xc2s100-pq208-5 -cm area -pr b -k 4 -c 100 -tx off -o pwm_map.ncd pwm.ngd pwm.pcf
Mapping Module pwm: DONE



Started process "Place & Route".





Constraints file: pwm.pcf

Loading device database for application Par from file "pwm_map.ncd".
   "pwm" is an NCD, version 2.38, device xc2s100, package pq208, speed -5
Loading device for application Par from file 'v100.nph' in environment
C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2004-06-25.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary: