automake.log

在xilinx的ise环境下用vhdl编写的一个时钟程序。

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
sec:Q                              | NONE                   | 19    |
clk                                | BUFGP                  | 31    |
I__n0006:O                         | NONE(*)(keyen_reg)     | 1     |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 15.911ns (Maximum Frequency: 62.850MHz)
   Minimum input arrival time before clock: 6.075ns
   Maximum output required time after clock: 16.133ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               15.911ns (Levels of Logic = 24)
  Source:            count_10
  Destination:       count_25
  Source Clock:      clk falling
  Destination Clock: clk falling

  Data Path: count_10 to count_25
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    FDR_1:C->Q            14   1.292   2.600  count_10 (count_10)
    LUT1_L:I0->LO          1   0.653   0.000  count_101 (count_101)
    MUXCY:S->O             1   0.784   0.000  Madd__old_count_1_inst_cy_14 (Madd__old_count_1_inst_cy_14)
    MUXCY:CI->O            1   0.050   0.000  Madd__old_count_1_inst_cy_15 (Madd__old_count_1_inst_cy_15)
    MUXCY:CI->O            1   0.050   0.000  Madd__old_count_1_inst_cy_16 (Madd__old_count_1_inst_cy_16)
    MUXCY:CI->O            1   0.050   0.000  Madd__old_count_1_inst_cy_17 (Madd__old_count_1_inst_cy_17)
    MUXCY:CI->O            1   0.050   0.000  Madd__old_count_1_inst_cy_18 (Madd__old_count_1_inst_cy_18)
    MUXCY:CI->O            1   0.050   0.000  Madd__old_count_1_inst_cy_19 (Madd__old_count_1_inst_cy_19)
    MUXCY:CI->O            1   0.050   0.000  Madd__old_count_1_inst_cy_20 (Madd__old_count_1_inst_cy_20)
    MUXCY:CI->O            1   0.050   0.000  Madd__old_count_1_inst_cy_21 (Madd__old_count_1_inst_cy_21)
    MUXCY:CI->O            1   0.050   0.000  Madd__old_count_1_inst_cy_22 (Madd__old_count_1_inst_cy_22)
    MUXCY:CI->O            1   0.050   0.000  Madd__old_count_1_inst_cy_23 (Madd__old_count_1_inst_cy_23)
    MUXCY:CI->O            1   0.050   0.000  Madd__old_count_1_inst_cy_24 (Madd__old_count_1_inst_cy_24)
    MUXCY:CI->O            1   0.050   0.000  Madd__old_count_1_inst_cy_25 (Madd__old_count_1_inst_cy_25)
    MUXCY:CI->O            1   0.050   0.000  Madd__old_count_1_inst_cy_26 (Madd__old_count_1_inst_cy_26)
    MUXCY:CI->O            1   0.050   0.000  Madd__old_count_1_inst_cy_27 (Madd__old_count_1_inst_cy_27)
    MUXCY:CI->O            1   0.050   0.000  Madd__old_count_1_inst_cy_28 (Madd__old_count_1_inst_cy_28)
    MUXCY:CI->O            1   0.050   0.000  Madd__old_count_1_inst_cy_29 (Madd__old_count_1_inst_cy_29)
    MUXCY:CI->O            1   0.050   0.000  Madd__old_count_1_inst_cy_30 (Madd__old_count_1_inst_cy_30)
    MUXCY:CI->O            1   0.050   0.000  Madd__old_count_1_inst_cy_31 (Madd__old_count_1_inst_cy_31)
    MUXCY:CI->O            0   0.050   0.000  Madd__old_count_1_inst_cy_32 (Madd__old_count_1_inst_cy_32)
    XORCY:CI->O            2   0.500   1.340  Madd__old_count_1_inst_sum_33 (N167)
    LUT2:I1->O             1   0.653   1.150  I_1_LUT_8 (N169)
    LUT4_D:I0->O           1   0.653   1.150  I_0_LUT_10 (N201)
    LUT2:I0->O            16   0.653   2.800  I__n0004 (N245)
    FDR_1:R                    0.783          count_25
    ----------------------------------------
    Total                     15.911ns (6.871ns logic, 9.040ns route)
                                       (43.2% logic, 56.8% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'sec:Q'
Offset:              6.075ns (Levels of Logic = 3)
  Source:            keyclr
  Destination:       min_13
  Destination Clock: sec:Q falling

  Data Path: keyclr to min_13
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    IBUF:I->O              5   0.924   1.740  keyclr_IBUF (keyclr_IBUF)
    LUT1:I0->O             1   0.653   0.000  I__n0008_F (N1347)
    MUXF5:I0->O            4   0.375   1.600  I__n0008 (N308)
    FDRE_1:R                   0.783          min_13
    ----------------------------------------
    Total                      6.075ns (2.735ns logic, 3.340ns route)
                                       (45.0% logic, 55.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Offset:              16.133ns (Levels of Logic = 5)
  Source:            count_10
  Destination:       lddat_7
  Source Clock:      clk falling

  Data Path: count_10 to lddat_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    FDR_1:C->Q            14   1.292   2.600  count_10 (count_10)
    LUT3:I2->O             1   0.653   0.000  Mmux_ledbuf_inst_lut3_0 (Mmux_ledbuf_xstmacro_int_tempname0)
    MUXF5:I0->O            8   0.375   2.050  Mmux_ledbuf_inst_mux_f5_0 (N359)
    LUT4:I0->O             1   0.653   1.150  Mrom__inst_lut4_7 (N145)
    LUT4:I0->O             1   0.653   1.150  I_lddat_7 (lddat_7_OBUF)
    OBUF:I->O                  5.557          lddat_7_OBUF (lddat_7)
    ----------------------------------------
    Total                     16.133ns (9.183ns logic, 6.950ns route)
                                       (56.9% logic, 43.1% route)

=========================================================================
CPU : 3.90 / 4.01 s | Elapsed : 4.00 / 4.00 s
 
--> 
EXEWRAP detected that program 'D:/xilinx_webpack/bin/nt/xst.exe' completed successfully.

Done: completed successfully.

Starting: 'exewrap @__ednTOngd_exewrap.rsp'


Starting: 'ngdbuild -f __ngdbuild.rsp '


Release 4.1WP3.x - ngdbuild E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
ERROR:Portability:138 - Invalid file format, check the command argument file
   "__ngdbuild.rsp".
Usage: ngdbuild [-p <partname>] {-sd <source_dir>} {-l <library>} [-ur
<rules_file[.urf]>] [-dd <output_dir>] [-r] [-a] [-u] [-nt timestamp|on|off]
[-uc <ucf_file[.ucf]>] [-aul] [-i] [-modular initial|module|assemble] [-quiet]
[-verbose] [-active <active_module_name>] [-pimpath <pimpath>] {-use_pim
<pim_module_name>} <design_name> [<ngd_file[.ngd]>]

      -p  partname     Use specified part type to implement the design
      -sd source_dir   Add "source_dir" to the list of directories
                       to search when resolving netlist file references
      -l library       Add "library" to the list of source libraries
                       passed to the netlisters
      -ur rules_file   User rules file for netlist launcher
      -dd output_dir   Directory to place intermediate .ngo files
      -nt value        NGO file generation
                       Options:       "timestamp", "on", "off"
                       -nt timestamp: Regenerate NGO only when source
                                      netlist is newer than existing
                                      NGO file (default)
                       -nt on:        Always regenerate NGO file from
                                      source design netlists
                       -nt off:       Do not regenerate NGO files
                                      which already exist. Build NGD
                                      file from existing NGO files
      -uc ucf_file     Use specified "User Constraint File".
                       The file <design_name>.ucf is used by default
                       if it is found in the local directory.
      -r               Ignore location constraints
      -aul             Allow unmatched LOC constraints
      -a               Infer pad components from ports in top-level EDIF
                       netlist (if any)
      -i               Ignore usage of default ucf file, if present
      -u               Allow unexpanded blocks in output NGD design.
                       During partial design assembly flow, it gets used
                       along with -modular assemble switch to consider
                       unexpanded blocks as unimplemented modules.
      -modular initial|module|assemble
                       Modular design flows:
         -modular initial
                       Modular design in initial budgeting mode
         -modular module -active <active_module_name>
                       Modular design in active module mode
            -active <active_module_name>
                       Specifies the name of active module.
         -modular assemble -pimpath <pimpath> -use_pim <pim_module_name>
                       Modular design in assembly mode
            -pimpath <pimpath>
                       Specifies directory contains PIMs.
            -use_pim <pim_module_name>
                       Specifies an instantiated module in a top level design.
                       -use_pim can be used multiple times to specify multiple 
                       instantiated modules.
                       if -use_pim is missing, all subdirectories located in 
                       <pimpath> directory, which contain a .ngo file with the 
                       same subdirectory name, will be considered as valid 
                       instantiated modules.
      -quiet           Only report Warning and Error messages
      -verbose         Reports all messages
NGDBUILD:  Translates and merges the various source files of a design into a
single "NGD" design database.
EXEWRAP detected a return code of '2' from program 'ngdbuild'

Done: failed with exit code: 0002.