frequ_er.vhd

这是一个频率产生的VHDL程序源码

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-- 	This is a auto_changable scale frequencer.The test range is from 1Hz to  99.9MHz,  --
--  specially write for GEXIN.FPGA/P844 development system. And this design  can  be   --
--  implemented in the ALTERA device--EPM7128SLC-15.								   --
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--follow is  frequency productor,produce different frequency impluse
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

ENTITY basifre_product IS
	PORT (                  clk_1kh  :	IN	std_logic;
			fre_100h,fre_10h,fre_1h  :	OUT		std_logic);
END basifre_product;
ARCHITECTURE stru OF basifre_product IS
	COMPONENT	cont10
		PORT(	clk,rst,en	:	IN	std_logic;
					count	:	OUT integer RANGE 0 TO 9 ;
					ca_rry	:	OUT	std_logic);
	END COMPONENT ;
SIGNAL				 vcc,gnd	:	std_logic;
SIGNAL	fre_100h_t,fre_10h_t	:	std_logic;
BEGIN
	vcc <= '1' ;
	gnd <= '0' ;
	u1	:	cont10	PORT MAP ( clk => clk_1kh    ,rst => gnd ,en => vcc ,ca_rry => fre_100h_t ) ;
	u2	:	cont10	PORT MAP ( clk => fre_100h_t ,rst => gnd ,en => vcc ,ca_rry => fre_10h_t  ) ;
	u3	:	cont10	PORT MAP ( clk => fre_10h_t  ,rst => gnd ,en => vcc ,ca_rry => fre_1h     ) ;	
	fre_100h  <= fre_100h_t ;
	fre_10h   <= fre_10h_t  ;
END stru;	

--follow is mux6_1,and output is a single impluse,namely, different basic frequency
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY mux_basifre IS
	PORT ( fre_1kh,fre_100h,fre_10h,fre_1h  :	IN 	std_logic ;
						rst_mux_basifre,en  :	IN 	std_logic ;
			    					sel_fre :	IN	integer RANGE 0 TO 3;
				    			  basi_fre  :   OUT std_logic );
END mux_basifre;
ARCHITECTURE beha_basifre OF mux_basifre  IS 
	COMPONENT single_clk
		PORT (cp,cd,en :    IN	std_logic;
				   q   :	OUT	std_logic);
	END COMPONENT ;
SIGNAL	basi_fre_tmp,vcc :	std_logic ;
BEGIN
	vcc <= '1' ;
	PROCESS(fre_1kh,fre_100h,fre_10h,fre_1h,en,sel_fre)
	BEGIN
		IF en = '0' THEN
			basi_fre_tmp <= '0' ;
		ELSE
			CASE sel_fre IS
				WHEN 0 =>	basi_fre_tmp <= fre_1h ;
				WHEN 1 =>	basi_fre_tmp <= fre_10h ;
				WHEN 2 =>	basi_fre_tmp <= fre_100h ;
				WHEN 3 =>	basi_fre_tmp <= fre_1kh ;
				WHEN OTHERS => basi_fre_tmp <= '0' ;
			END CASE ;
		END IF ;
	END PROCESS ;
	single_impluse : single_clk 
		PORT MAP (cp => basi_fre_tmp, cd => rst_mux_basifre,en => vcc, q => basi_fre);
END beha_basifre ;

--follow is single impluse productor,
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY t IS
	PORT (cp,cd :	IN 	 std_logic;
			 q  :	OUT	 std_logic);
END t;
ARCHITECTURE beha OF t  IS 
SIGNAL qq :	 std_logic;
BEGIN
	PROCESS (cp,cd)
	BEGIN
		IF cd = '1' THEN
			qq<= '0' ;
		ELSIF rising_edge(cp) THEN
			qq<= NOT qq ;
		END IF  ;
	END PROCESS ;
	q<=qq;
END beha;

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY d IS
	PORT (cp,cd :	IN	std_logic;
			q   :	OUT	std_logic);
END d;
ARCHITECTURE beha OF d IS 
SIGNAL qq :	std_logic;
BEGIN
	PROCESS (cp,cd)
	BEGIN
		IF cd = '1' THEN
			qq<= '0' ;
		ELSIF rising_edge(cp) THEN
			qq<= '1';
		END IF ;
	END PROCESS;
	q<=qq;
END beha;

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY single_clk IS
	PORT (cp,cd,en:	IN	std_logic;
			q   :	OUT	std_logic);
END single_clk;
ARCHITECTURE stru OF single_clk IS
	COMPONENT t
		PORT (cp,cd :	IN	std_logic;
				q   :	OUT	std_logic);
	END COMPONENT ;
	COMPONENT d 
		PORT (cp,cd :	IN	std_logic;
				q   :	OUT	std_logic);
	END COMPONENT ;
SIGNAL q1,q2,q11,cpt :	 std_logic;
BEGIN
	q11 <=  NOT q1;
	cpt <=  cp AND en ;
	u1: t   PORT MAP (cp,cd,q1);
	u2: d   PORT MAP ( q11,cd,q2);				
	q <= q1 AND (NOT q2) ;
END stru;

--FOLLOW IS EXTER FREQUENCY CPUMTER
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

ENTITY exter_fre IS
	PORT (  clk_exter,rst_ex_fre,en :	IN	std_logic ;
			cont1,cont2,cont3,cont4	:	OUT	integer	RANGE 0 TO 9 ;
			       ex_ov_l,ex_ov_h  :	OUT	std_logic);
END exter_fre;
ARCHITECTURE stru OF exter_fre IS
	COMPONENT	cont10
		PORT(		clk,rst,en	:	IN	std_logic;
						count	:	OUT integer RANGE 0 TO 9 ;
			 			ca_rry	:	OUT	std_logic);
	END COMPONENT ;
SIGNAL	carry1,carry2,carry3 :	std_logic;
SIGNAL		cont4_t,cont3_t	 :	integer RANGE 0 TO 9 ;
SIGNAL			  ex_ov_h_t  :	std_logic;
BEGIN
	u1	:	cont10	PORT MAP (clk_exter  , rst_ex_fre , en ,  cont1  ,  carry1    ) ;	
	u2	:	cont10	PORT MAP ( carry1    , rst_ex_fre , en ,  cont2  ,  carry2    ) ;
	u3	:	cont10	PORT MAP ( carry2    , rst_ex_fre , en ,  cont3_t,  carry3    ) ;
	u4	:	cont10	PORT MAP ( carry3    , rst_ex_fre , en ,  cont4_t,  ex_ov_h_t ) ;
	cont3 <= cont3_t ;
	cont4 <= cont4_t ;	
	ex_ov_l <= '1' WHEN (cont3_t = 0) AND (cont4_t = 0) ELSE
				   '0' ; 
	PROCESS (ex_ov_h_t,rst_ex_fre)
	BEGIN
		IF rst_ex_fre = '1' THEN
			ex_ov_h <= '0' ;
		ELSIF rising_edge(ex_ov_h_t) THEN
			ex_ov_h <= '1' ;
		END IF ;
	END PROCESS ;
						   
END stru;	


--follow is 10 counter
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

ENTITY cont10 IS
	PORT(	clk,rst,en	:	IN	std_logic;
				count	:	OUT integer RANGE 0 TO 9 ;
				ca_rry	:	OUT	std_logic);
END cont10;
ARCHITECTURE beha OF cont10 IS
SIGNAL	count_tem :  integer RANGE 0 TO 9 ;
BEGIN
	PROCESS(clk,rst,en)
	BEGIN
		IF rst = '1' THEN
			 count_tem <= 0 ;
			    ca_rry <= '0' ;
		ELSIF rising_edge(clk) THEN
			IF 	en = '1' THEN
				IF count_tem = 9 THEN
					count_tem  <= 0 ;
					    ca_rry <= '1' ;
				ELSE
 					count_tem  <= count_tem + 1 ;
 					    ca_rry <= '0' ;
 				END IF;
 			END IF;
		END IF;
		count <= count_tem ;
	END PROCESS;
END beha;

--follow is cotroler,it produce istructions to control other function block
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;

ENTITY controler IS
	PORT ( 	   fre_10h,clk_8kh	:	IN	std_logic ;
			       measure_end	:	IN	std_logic ;
			   ex_ov_l,ex_ov_h :	IN	std_logic ;
   		   measure,display,rst  :	OUT	std_logic ;
   			    		 alarm	:	OUT	std_logic ;
				   sel_basifre	:	OUT	integer RANGE 0 TO 3 );
END controler;
ARCHITECTURE beha_control OF controler IS
	COMPONENT single_clk
		PORT (cp,cd,en:	IN	std_logic;
				    q :	OUT	std_logic);
	END COMPONENT ;

SIGNAL vcc,ov_l,ov_h,pc,display_t,display_end :	 std_logic;
SIGNAL	display_hold_cont	:	integer RANGE 0 TO 9 ;
SIGNAL	     sel_scale_t	:	integer RANGE 0 TO 3 ;
BEGIN
	vcc <= '1' ;
	PROCESS (measure_end,ex_ov_l,ex_ov_h)
	BEGIN
		IF falling_edge(measure_end) THEN
			ov_l <= ex_ov_l;
			ov_h <= ex_ov_h ;
		END IF ;
	END PROCESS ;
	
	PROCESS (measure_end,clk_8kh)
	BEGIN
		IF measure_end = '1' THEN
			pc <= '0' ;
		ELSIF rising_edge(clk_8kh) THEN
			pc <= not pc ;
		END IF ;
	END PROCESS ;
	rst_out : single_clk  	PORT MAP (pc, measure_end, vcc, rst);
	
	PROCESS (pc,ov_h,ov_l,display_end)
	BEGIN
		IF rising_edge(pc) THEN
			IF  ov_h = '1' THEN
				display_t <= '0' ;
				measure <= '1' ;
				IF  sel_scale_t /= 3 THEN
			    	sel_scale_t <= sel_scale_t + 1;
					alarm <= '0' ;
				ELSE
					alarm <= '1' ;
				END IF ;
			 ELSIF ov_l = '1' THEN
			 	display_t <= '0' ;
			 	measure <= '1' ;
				IF  sel_scale_t /= 0 THEN
			    	sel_scale_t <= sel_scale_t - 1;
				END IF ;
			 ELSE
			 	display_t <= '1' ;
			 	IF  display_end = '1' THEN
			 		measure <= '1' ;
			 	ELSE
			 		measure <= '0' ;
			 	END IF ;
			 END IF ;
		END IF ;
		sel_basifre <= sel_scale_t ;
	END PROCESS ;
	display <= display_t ;
	PROCESS (display_t,measure_end,fre_10h)
	BEGIN
		IF  measure_end = '1' THEN
			display_hold_cont <= 0 ;
		ELSIF rising_edge(fre_10h) THEN
			IF display_t = '1' THEN
				IF display_hold_cont = 9 THEN
					display_hold_cont <= 0 ;
					display_end <= '1' ;
				ELSE
					display_hold_cont <= display_hold_cont + 1 ;
					display_end <= '0' ;
				END IF ;
			END IF ;
		END IF ;
	END PROCESS ;
END ;

--follow is display block, 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

ENTITY display IS
	PORT(   clk_8kh, clk_1kh,display,measure_end  :	  IN	std_logic;
			 ex_cont1,ex_cont2,ex_cont3,ex_cont4  :	  IN	integer RANGE 0 TO 9 ;
			    	                   sel_scale  :   IN	integer RANGE 0 TO 3 ;
		          sel_led_line10, sel_led_line32  :	  OUT std_logic_vector(1 downto 0);