pci_parity_check.v

用verilog编写的pci——rtl级。

wire par_out_only = data_par ^ par_cbe_out ;

pci_par_crit par_gen
(
    .par_out        (pci_par_out),
    .par_out_in     (par_out_only),
    .pci_cbe_en_in  (pci_cbe_en_in),
    .data_par_in    (data_par),
    .pci_cbe_in     (pci_cbe_in_in)
) ;

// PAR enable = ad output enable delayed by one clock
assign pci_par_en_out = pci_ad_en_in ;

/*=======================================================================================================================
Parity checker - parity is checked on every clock cycle. When parity error is detected, appropriate action is taken
to signal address parity errors on SERR if enabled and data parity errors on PERR# if enabled. Logic also drives
outputs to configuration space to set appropriate status bits if parity error is detected. PAR signal is checked on
master read operations or writes through pci target. Master read is performed when master drives irdy output and
doesn't drive ad lines. Writes through target are performed when target is driving trdy and doesn't drive ad lines.
=======================================================================================================================*/

// equation indicating whether to check and generate or not PERR# signal on next cycle
wire perr_generate =  ~pci_par_en_in && ~pci_ad_en_in                   // par was not generated on this cycle, so it should be checked
                      && ((pci_irdy_en_in && ~pci_trdy_reg_in) ||       // and master is driving irdy and target is signaling ready
                          (pci_trdy_en_in && ~pci_irdy_reg_in)) ;       // or target is driving trdy and master is signaling ready

wire data_in_par = (pci_ad_reg_in[31] ^ pci_ad_reg_in[30] ^ pci_ad_reg_in[29] ^ pci_ad_reg_in[28]) ^
                   (pci_ad_reg_in[27] ^ pci_ad_reg_in[26] ^ pci_ad_reg_in[25] ^ pci_ad_reg_in[24]) ^
                   (pci_ad_reg_in[23] ^ pci_ad_reg_in[22] ^ pci_ad_reg_in[21] ^ pci_ad_reg_in[20]) ^
                   (pci_ad_reg_in[19] ^ pci_ad_reg_in[18] ^ pci_ad_reg_in[17] ^ pci_ad_reg_in[16]) ^
                   (pci_ad_reg_in[15] ^ pci_ad_reg_in[14] ^ pci_ad_reg_in[13] ^ pci_ad_reg_in[12]) ^
                   (pci_ad_reg_in[11] ^ pci_ad_reg_in[10] ^ pci_ad_reg_in[9]  ^ pci_ad_reg_in[8])  ^
                   (pci_ad_reg_in[7]  ^ pci_ad_reg_in[6]  ^ pci_ad_reg_in[5]  ^ pci_ad_reg_in[4])  ^
                   (pci_ad_reg_in[3]  ^ pci_ad_reg_in[2]  ^ pci_ad_reg_in[1]  ^ pci_ad_reg_in[0]) ;

//wire perr = (cbe_par_reg ^ pci_par_in ^ data_in_par) ;
wire perr ;
wire perr_n ;
wire perr_en ;

assign pci_perr_out = perr_n ;

// parity error output assignment
//assign pci_perr_out = ~(perr && perr_generate) ;

wire non_critical_par = par_cbe_in ^ data_in_par ;

pci_perr_crit perr_crit_gen
(
    .perr_out           (perr),
    .perr_n_out         (perr_n),
    .non_critical_par_in(non_critical_par),
    .pci_par_in         (pci_par_in),
    .perr_generate_in   (perr_generate)
) ;

// PERR# enable
wire pci_perr_en_reg ;
pci_perr_en_crit perr_en_crit_gen
(
    .reset_in               (reset_in),
    .clk_in                 (clk_in),
    .perr_en_out            (pci_perr_en_out),
    .perr_en_reg_out        (pci_perr_en_reg),
    .non_critical_par_in    (non_critical_par),
    .pci_par_in             (pci_par_in),
    .perr_generate_in       (perr_generate),
    .par_err_response_in    (par_err_response_in)
) ;

// address phase decoding
always@(posedge reset_in or posedge clk_in)
begin
    if (reset_in)
        frame_dec2 <= #`FF_DELAY 1'b0 ;
    else
        frame_dec2 <= #`FF_DELAY pci_frame_reg_in ;
end

// address phase parity error checking - done after address phase is detected - which is - when bridge's master is not driving frame,
// frame was asserted on previous cycle and was not asserted two cycles before.
wire check_for_serr_on_first = ~pci_frame_reg_in && frame_dec2  && ~pci_frame_en_in ;

reg  check_for_serr_on_second ;
always@(posedge reset_in or posedge clk_in)
begin
    if ( reset_in )
        check_for_serr_on_second <= #`FF_DELAY 1'b0 ;
    else
        check_for_serr_on_second <= #`FF_DELAY check_for_serr_on_first && ( pci_cbe_reg_in == `BC_DUAL_ADDR_CYC ) ;
end

wire check_for_serr = check_for_serr_on_first || check_for_serr_on_second ;

wire serr_generate = check_for_serr && serr_enable_in && par_err_response_in ;

pci_serr_en_crit serr_en_crit_gen
(
    .serr_en_out        (pci_serr_en_out),
    .pci_par_in         (pci_par_in),
    .non_critical_par_in(non_critical_par),
    .serr_generate_in   (serr_generate)
);


// serr is enabled only for reporting errors - route this signal to configuration space
assign sig_serr_out = pci_serr_en_in ;

// SERR# output is always 0, just enable is driven apropriately
pci_serr_crit serr_crit_gen
(
    .serr_out               (pci_serr_out),
    .non_critical_par_in    (non_critical_par),
    .pci_par_in             (pci_par_in),
    .serr_check_in          (check_for_serr)
);

/*=======================================================================================================================================
    Synchronizing mechanism detecting what is supposed to be done - PERR# generation or PERR# checking
=======================================================================================================================================*/
// perr should be checked one clock after PAR is generated
always@(posedge reset_in or posedge clk_in)
begin
    if ( reset_in )
        check_perr <= #`FF_DELAY 1'b0 ;
    else
        check_perr <= #`FF_DELAY pci_par_en_in ;
end

wire perr_sampled_in = ~pci_perr_in && check_perr ;
reg perr_sampled ;
always@(posedge reset_in or posedge clk_in)
begin
    if (reset_in)
        perr_sampled <= #`FF_DELAY 1'b0 ;
    else
        perr_sampled <= #`FF_DELAY perr_sampled_in ;
end

// assign output for parity error detected bit
assign par_err_detect_out = ~pci_serr_out_in || ~pci_perr_out_in ;//|| perr_sampled ; MihaD - removed - detected parity error is set only during Master Reads or Target Writes

// FF indicating that that last operation was done as bus master
reg frame_and_irdy_en_prev      ;
reg frame_and_irdy_en_prev_prev ;
reg master_perr_report ;
always@(posedge reset_in or posedge clk_in)
begin
    if ( reset_in )
    begin
        master_perr_report          <= #`FF_DELAY 1'b0 ;
        frame_and_irdy_en_prev      <= #`FF_DELAY 1'b0 ;
        frame_and_irdy_en_prev_prev <= #`FF_DELAY 1'b0 ;
    end
    else
    begin
        master_perr_report          <= #`FF_DELAY frame_and_irdy_en_prev_prev ;
        frame_and_irdy_en_prev      <= #`FF_DELAY pci_irdy_en_in && pci_frame_en_in ;
        frame_and_irdy_en_prev_prev <= #`FF_DELAY frame_and_irdy_en_prev ;
    end
end

assign perr_mas_detect_out = master_perr_report && ( (par_err_response_in && perr_sampled) || pci_perr_en_reg ) ;

endmodule