📄 pci_conf_space.v
字号:
`endif
/*###########################################################################################################
-------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------*/
`ifdef NO_CNF_IMAGE // if IMAGE0 is assigned as general image space
assign r_conf_data_out = 32'h0000_0000 ;
`else
always@(r_conf_address_in or
status_bit15_11 or status_bit8 or r_status_bit4 or command_bit8 or command_bit6 or command_bit2_0 or
latency_timer or cache_line_size_reg or r_vendor_id or r_device_id or r_revision_id or
r_subsys_vendor_id or r_subsys_id or r_max_lat or r_min_gnt or
pci_ba0_bit31_8 or
pci_img_ctrl0_bit2_1 or pci_am0 or pci_ta0 or pci_ba0_bit0 or
pci_img_ctrl1_bit2_1 or pci_am1 or pci_ta1 or pci_ba1_bit31_8 or pci_ba1_bit0 or
pci_img_ctrl2_bit2_1 or pci_am2 or pci_ta2 or pci_ba2_bit31_8 or pci_ba2_bit0 or
pci_img_ctrl3_bit2_1 or pci_am3 or pci_ta3 or pci_ba3_bit31_8 or pci_ba3_bit0 or
pci_img_ctrl4_bit2_1 or pci_am4 or pci_ta4 or pci_ba4_bit31_8 or pci_ba4_bit0 or
pci_img_ctrl5_bit2_1 or pci_am5 or pci_ta5 or pci_ba5_bit31_8 or pci_ba5_bit0 or
interrupt_line or
pci_err_cs_bit31_24 or pci_err_cs_bit10 or pci_err_cs_bit9 or pci_err_cs_bit8 or pci_err_cs_bit0 or
pci_err_addr or pci_err_data or
wb_ba0_bit31_12 or wb_ba0_bit0 or
wb_img_ctrl1_bit2_0 or wb_ba1_bit31_12 or wb_ba1_bit0 or wb_am1 or wb_ta1 or
wb_img_ctrl2_bit2_0 or wb_ba2_bit31_12 or wb_ba2_bit0 or wb_am2 or wb_ta2 or
wb_img_ctrl3_bit2_0 or wb_ba3_bit31_12 or wb_ba3_bit0 or wb_am3 or wb_ta3 or
wb_img_ctrl4_bit2_0 or wb_ba4_bit31_12 or wb_ba4_bit0 or wb_am4 or wb_ta4 or
wb_img_ctrl5_bit2_0 or wb_ba5_bit31_12 or wb_ba5_bit0 or wb_am5 or wb_ta5 or
wb_err_cs_bit31_24 or /*wb_err_cs_bit10 or*/ wb_err_cs_bit9 or wb_err_cs_bit8 or wb_err_cs_bit0 or
wb_err_addr or wb_err_data or
cnf_addr_bit23_2 or cnf_addr_bit0 or icr_bit31 or icr_bit4_3 or icr_bit2_0 or isr_bit4_3 or isr_bit2_0
`ifdef PCI_CPCI_HS_IMPLEMENT
or hs_ins or hs_ext or hs_pi or hs_loo or hs_eim or hs_cap_id
`endif
`ifdef PCI_SPOCI
or spoci_cs_nack or spoci_cs_write or spoci_cs_read or spoci_cs_adr or spoci_cs_dat
`endif
)
begin
case (r_conf_address_in[9:2])
// PCI header - configuration space
8'h0: r_conf_data_out = { r_device_id, r_vendor_id } ;
8'h1: r_conf_data_out = { status_bit15_11, r_status_bit10_9, status_bit8, r_status_bit7, 1'h0, r_status_bit5, r_status_bit4,
4'h0, 7'h00, command_bit8, 1'h0, command_bit6, 3'h0, command_bit2_0 } ;
8'h2: r_conf_data_out = { r_class_code, r_revision_id } ;
8'h3: r_conf_data_out = { 8'h00, r_header_type, latency_timer, cache_line_size_reg } ;
8'h4:
begin
`ifdef HOST
`ifdef NO_CNF_IMAGE
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba0_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
r_conf_data_out[0] = pci_ba0_bit0 & pci_am0[31];
`else
r_conf_data_out[31:12] = pci_ba0_bit31_8[31:12] ;
r_conf_data_out[11: 0] = 12'h000 ;
`endif
`endif
`ifdef GUEST
r_conf_data_out[31:12] = pci_ba0_bit31_8[31:12] ;
r_conf_data_out[11: 0] = 12'h000 ;
`endif
end
8'h5:
begin
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba1_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
r_conf_data_out[0] = pci_ba1_bit0 & pci_am1[31];
end
8'h6:
begin
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba2_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
r_conf_data_out[0] = pci_ba2_bit0 & pci_am2[31];
end
8'h7:
begin
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba3_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
r_conf_data_out[0] = pci_ba3_bit0 & pci_am3[31];
end
8'h8:
begin
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba4_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
r_conf_data_out[0] = pci_ba4_bit0 & pci_am4[31];
end
8'h9:
begin
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba5_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
pci_am5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
r_conf_data_out[0] = pci_ba5_bit0 & pci_am5[31];
end
8'hB:
begin
r_conf_data_out = {r_subsys_id, r_subsys_vendor_id} ;
end
`ifdef PCI_CPCI_HS_IMPLEMENT
8'hD:
begin
r_conf_data_out = {24'h0000_00, `PCI_CAP_PTR_VAL} ;
end
`endif
8'hf: r_conf_data_out = { r_max_lat, r_min_gnt, r_interrupt_pin, interrupt_line } ;
`ifdef PCI_CPCI_HS_IMPLEMENT
(`PCI_CAP_PTR_VAL >> 2):
begin
r_conf_data_out = {8'h00, hs_ins, hs_ext, hs_pi, hs_loo, 1'b0, hs_eim, 1'b0, 8'h00, hs_cap_id} ;
end
`endif
// PCI target - configuration space
{2'b01, `P_IMG_CTRL0_ADDR}: r_conf_data_out = { 29'h00000000, pci_img_ctrl0_bit2_1, 1'h0 } ;
{2'b01, `P_BA0_ADDR} :
begin
`ifdef HOST
`ifdef NO_CNF_IMAGE
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba0_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
r_conf_data_out[0] = pci_ba0_bit0 & pci_am0[31];
`else
r_conf_data_out[31:12] = pci_ba0_bit31_8[31:12] ;
r_conf_data_out[11: 0] = 12'h000 ;
`endif
`endif
`ifdef GUEST
r_conf_data_out[31:12] = pci_ba0_bit31_8[31:12] ;
r_conf_data_out[11: 0] = 12'h000 ;
`endif
end
{2'b01, `P_AM0_ADDR}:
begin
`ifdef HOST
`ifdef NO_CNF_IMAGE
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
`else
r_conf_data_out[31:12] = pci_am0[31:12] ;
r_conf_data_out[11: 0] = 12'h000 ;
`endif
`endif
`ifdef GUEST
r_conf_data_out[31:12] = pci_am0[31:12] ;
r_conf_data_out[11: 0] = 12'h000 ;
`endif
end
{2'b01, `P_TA0_ADDR}:
begin
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
end
{2'b01, `P_IMG_CTRL1_ADDR}: r_conf_data_out = { 29'h00000000, pci_img_ctrl1_bit2_1, 1'h0 } ;
{2'b01, `P_BA1_ADDR}:
begin
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba1_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
r_conf_data_out[0] = pci_ba1_bit0 & pci_am1[31];
end
{2'b01, `P_AM1_ADDR}:
begin
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
end
{2'b01, `P_TA1_ADDR}:
begin
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
end
{2'b01, `P_IMG_CTRL2_ADDR}: r_conf_data_out = { 29'h00000000, pci_img_ctrl2_bit2_1, 1'h0 } ;
{2'b01, `P_BA2_ADDR}:
begin
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba2_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
r_conf_data_out[0] = pci_ba2_bit0 & pci_am2[31];
end
{2'b01, `P_AM2_ADDR}:
begin
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
end
{2'b01, `P_TA2_ADDR}:
begin
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
end
{2'b01, `P_IMG_CTRL3_ADDR}: r_conf_data_out = { 29'h00000000, pci_img_ctrl3_bit2_1, 1'h0 } ;
{2'b01, `P_BA3_ADDR}:
begin
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba3_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
r_conf_data_out[0] = pci_ba3_bit0 & pci_am3[31];
end
{2'b01, `P_AM3_ADDR}:
begin
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
end
{2'b01, `P_TA3_ADDR}:
begin
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
end
{2'b01, `P_IMG_CTRL4_ADDR}: r_conf_data_out = { 29'h00000000, pci_img_ctrl4_bit2_1, 1'h0 } ;
{2'b01, `P_BA4_ADDR}:
begin
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba4_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
r_conf_data_out[0] = pci_ba4_bit0 & pci_am4[31];
end
{2'b01, `P_AM4_ADDR}:
begin
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
end
{2'b01, `P_TA4_ADDR}:
begin
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
end
{2'b01, `P_IMG_CTRL5_ADDR}: r_conf_data_out = { 29'h00000000, pci_img_ctrl5_bit2_1, 1'h0 } ;
{2'b01, `P_BA5_ADDR}:
begin
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba5_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
pci_am5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
r_conf_data_out[0] = pci_ba5_bit0 & pci_am5[31];
end
{2'b01, `P_AM5_ADDR}:
begin
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
end
{2'b01, `P_TA5_ADDR}:
begin
r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
end
{2'b01, `P_ERR_CS_ADDR}: r_conf_data_out = { pci_err_cs_bit31_24, 13'h0000, pci_err_cs_bit10, pci_err_cs_bit9,
pci_err_cs_bit8, 7'h00, pci_err_cs_bit0 } ;
{2'b01, `P_ERR_ADDR_ADDR}: r_conf_data_out = pci_err_addr ;
{2'b01, `P_ERR_DATA_ADDR}: r_conf_data_out = pci_err_data ;
// WB slave - configuration space
{2'b01, `WB_CONF_SPC_BAR_ADDR}: r_conf_data_out = { wb_ba0_bit31_12, 11'h000, wb_ba0_bit0 } ;
{2'b01, `W_IMG_CTRL1_ADDR}: r_conf_data_out = { 29'h00000000, wb_img_ctrl1_bit2_0 } ;
{2'b01, `W_BA1_ADDR}:
begin
r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ba1_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] &
wb_am1[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
r_conf_data_out[0] = wb_ba1_bit0 ;
end
{2'b01, `W_AM1_ADDR}:
begin
r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_am1[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
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