pci_conf_space.v

用verilog编写的pci——rtl级。

			reg		[31 :  8]	pci_ta3 ;
`else
            wire	[2 : 1]		pci_img_ctrl3_bit2_1 = 2'b00 ;
			wire	[31 :  8]	pci_ba3_bit31_8 = 24'h0000_00 ;
            wire				pci_ba3_bit0 = 1'b0 ;
            wire	[31 :  8]	pci_am3 = 24'h0000_00 ;
            wire	[31 :  8]	pci_ta3 = 24'h0000_00 ;
`endif
`ifdef		PCI_IMAGE4
			reg		[2 : 1]		pci_img_ctrl4_bit2_1 ;
			reg		[31 :  8]	pci_ba4_bit31_8 ;
	`ifdef	HOST
			reg					pci_ba4_bit0 ;
	`else
			wire				pci_ba4_bit0 = `PCI_BA4_MEM_IO ;
	`endif
			reg		[31 :  8]	pci_am4 ;
			reg		[31 :  8]	pci_ta4 ;
`else
            wire	[2 : 1]		pci_img_ctrl4_bit2_1 = 2'b00 ;
			wire	[31 :  8]	pci_ba4_bit31_8 = 24'h0000_00 ;
            wire				pci_ba4_bit0 = 1'b0 ;
            wire	[31 :  8]	pci_am4 = 24'h0000_00 ;
            wire	[31 :  8]	pci_ta4 = 24'h0000_00 ;
`endif
`ifdef		PCI_IMAGE5
			reg		[2 : 1]		pci_img_ctrl5_bit2_1 ;
			reg		[31 :  8]	pci_ba5_bit31_8 ;
	`ifdef	HOST
			reg					pci_ba5_bit0 ;
	`else
			wire				pci_ba5_bit0 = `PCI_BA5_MEM_IO ;
	`endif
			reg		[31 :  8]	pci_am5 ;
			reg		[31 :  8]	pci_ta5 ;
`else
            wire	[2 : 1]		pci_img_ctrl5_bit2_1 = 2'b00 ;
			wire	[31 :  8]	pci_ba5_bit31_8 = 24'h0000_00 ;
            wire				pci_ba5_bit0 = 1'b0 ;
            wire	[31 :  8]	pci_am5 = 24'h0000_00 ;
            wire	[31 :  8]	pci_ta5 = 24'h0000_00 ;
`endif
			reg		[31 : 24]	pci_err_cs_bit31_24 ;
			reg					pci_err_cs_bit10 ;
			reg					pci_err_cs_bit9 ;
			reg					pci_err_cs_bit8 ;
			reg					pci_err_cs_bit0 ;
			reg		[31 : 0]	pci_err_addr ;
			reg		[31 : 0]	pci_err_data ;


/*###########################################################################################################
-------------------------------------------------------------------------------------------------------------
WISHBONE Slave configuration registers
	There are also some registers with NOT all bits implemented and therefor uses _bitX or _bitX2_X1 to
	sign which bit or range of bits are implemented. Some special cases and examples are described below!
-------------------------------------------------------------------------------------------------------------
###########################################################################################################*/

/*-----------------------------------------------------------------------------------------------------------
[800h-85Ch]
	Depending on defines (WB_IMAGE1 or .. or WB_IMAGE4 or WB_IMAGE5) in constants.v file, there are
	registers corresponding to each IMAGE defined to REG and parameter wb_image_X assigned to '1'.
	The maximum number of images is "6". By default there are first two images used and the first (WB_IMAGE0)
	is assigned to Configuration space! With a 'define' WB_IMAGEx you choose the number of used WB IMAGES in
	a bridge without WB_IMAGE0 (e.g. WB_IMAGE3 tells, that WB_IMAGE1, WB_IMAGE2 and WB_IMAGE3 are used for
	mapping the space from PCI to WB. Offcourse, WB_IMAGE0 is assigned to Configuration space). That leave
	us WB_IMAGE5 as the maximum number of images.

	When error occurs, WISHBONE ERR_ADDR and ERR_DATA registers stores address and data on the bus that
	caused error. While ERR_CS register stores Byte Enables and Bus Command in the MSByte. In bits 10, 9
	and 8 it reports Retry Counter Expired (for posted writes), Error Source (Master Abort) and Error
	Report Signal (signals that error has occured) respectively. With bit 0 we enable Error Reporting
	mechanism.
-----------------------------------------------------------------------------------------------------------*/
// WB_IMAGE0 is always assigned to config. space or is not used
			wire	[2 : 0]		wb_img_ctrl0_bit2_0 = 3'b000 ; // NO addr.transl., pre-fetch and read-line
			wire	[31 : 12]	wb_ba0_bit31_12 = `WB_CONFIGURATION_BASE ;
			wire				wb_ba0_bit0 = 0 ; // config. space is MEMORY space
			wire	[31 : 12]	wb_am0 = `WB_AM0 ; // 4KBytes of configuration space is minimum
			wire	[31 : 12]	wb_ta0 = 20'h0000_0 ; // NO address translation needed
// WB_IMAGE1 is included by default meanwhile others are optional !
			reg		[2 : 0]		wb_img_ctrl1_bit2_0 ;
			reg		[31 : 12]	wb_ba1_bit31_12 ;
			reg					wb_ba1_bit0 ;
			reg		[31 : 12]	wb_am1 ;
			reg		[31 : 12]	wb_ta1 ;
`ifdef		WB_IMAGE2
			reg		[2 : 0]		wb_img_ctrl2_bit2_0 ;
			reg		[31 : 12]	wb_ba2_bit31_12 ;
			reg					wb_ba2_bit0 ;
			reg		[31 : 12]	wb_am2 ;
			reg		[31 : 12]	wb_ta2 ;
`else
            wire	[2 : 0]		wb_img_ctrl2_bit2_0 = 3'b000 ;
			wire	[31 : 12]	wb_ba2_bit31_12 = 20'h0000_0 ;
            wire				wb_ba2_bit0 = 1'b0 ;
            wire	[31 : 12]	wb_am2 = 20'h0000_0 ;
            wire	[31 : 12]	wb_ta2 = 20'h0000_0 ;
`endif
`ifdef		WB_IMAGE3
			reg		[2 : 0]		wb_img_ctrl3_bit2_0 ;
			reg		[31 : 12]	wb_ba3_bit31_12 ;
			reg					wb_ba3_bit0 ;
			reg		[31 : 12]	wb_am3 ;
			reg		[31 : 12]	wb_ta3 ;
`else
            wire	[2 : 0]		wb_img_ctrl3_bit2_0 = 3'b000 ;
			wire	[31 : 12]	wb_ba3_bit31_12 = 20'h0000_0 ;
            wire				wb_ba3_bit0 = 1'b0 ;
            wire	[31 : 12]	wb_am3 = 20'h0000_0 ;
            wire	[31 : 12]	wb_ta3 = 20'h0000_0 ;
`endif
`ifdef		WB_IMAGE4
			reg		[2 : 0]		wb_img_ctrl4_bit2_0 ;
			reg		[31 : 12]	wb_ba4_bit31_12 ;
			reg					wb_ba4_bit0 ;
			reg		[31 : 12]	wb_am4 ;
			reg		[31 : 12]	wb_ta4 ;
`else
            wire	[2 : 0]		wb_img_ctrl4_bit2_0 = 3'b000 ;
			wire	[31 : 12]	wb_ba4_bit31_12 = 20'h0000_0 ;
            wire				wb_ba4_bit0 = 1'b0 ;
            wire	[31 : 12]	wb_am4 = 20'h0000_0 ;
            wire	[31 : 12]	wb_ta4 = 20'h0000_0 ;
`endif
`ifdef		WB_IMAGE5
			reg		[2 : 0]		wb_img_ctrl5_bit2_0 ;
			reg		[31 : 12]	wb_ba5_bit31_12 ;
			reg					wb_ba5_bit0 ;
			reg		[31 : 12]	wb_am5 ;
			reg		[31 : 12]	wb_ta5 ;
`else
            wire	[2 : 0]		wb_img_ctrl5_bit2_0 = 3'b000 ;
			wire	[31 : 12]	wb_ba5_bit31_12 = 20'h0000_0 ;
            wire				wb_ba5_bit0 = 1'b0 ;
            wire	[31 : 12]	wb_am5 = 20'h0000_0 ;
            wire	[31 : 12]	wb_ta5 = 20'h0000_0 ;
`endif
			reg		[31 : 24]	wb_err_cs_bit31_24 ;
/*			reg					wb_err_cs_bit10 ;*/
			reg					wb_err_cs_bit9 ;
			reg					wb_err_cs_bit8 ;
			reg					wb_err_cs_bit0 ;
			reg		[31 : 0]	wb_err_addr ;
			reg		[31 : 0]	wb_err_data ;


/*###########################################################################################################
-------------------------------------------------------------------------------------------------------------
Configuration Cycle address register
	There are also some registers with NOT all bits implemented and therefor uses _bitX or _bitX2_X1 to
	sign which bit or range of bits are implemented.
-------------------------------------------------------------------------------------------------------------
###########################################################################################################*/

/*-----------------------------------------------------------------------------------------------------------
[860h-868h]
	PCI bridge must ignore Type 1 configuration cycles (Master Abort) since they are used for PCI to PCI
	bridges. This is single function device, that means responding on configuration cycles to all functions
	(or responding only to function 0). Configuration address register for generating configuration cycles
	is prepared for all options (it includes Bus Number, Device, Function, Offset and Type).
	Interrupt acknowledge register stores interrupt vector data returned during Interrupt Acknowledge cycle.
-----------------------------------------------------------------------------------------------------------*/
`ifdef		HOST
			reg		[23 : 2]	cnf_addr_bit23_2 ;
			reg					cnf_addr_bit0 ;
`else // GUEST
			wire	[23 : 2]	cnf_addr_bit23_2	= 22'h0 ;
			wire				cnf_addr_bit0		= 1'b0 ;
`endif
			// reg	[31 : 0]	cnf_data ;		IMPLEMENTED elsewhere !!!!!
			// reg	[31 : 0]	int_ack ;		IMPLEMENTED elsewhere !!!!!


/*###########################################################################################################
-------------------------------------------------------------------------------------------------------------
General Interrupt registers
	There are also some registers with NOT all bits implemented and therefor uses _bitX or _bitX2_X1 to
	sign which bit or range of bits are implemented.
-------------------------------------------------------------------------------------------------------------
###########################################################################################################*/

/*-----------------------------------------------------------------------------------------------------------
[FF8h-FFCh]
	Bit 31 in the Interrupt Control register is set by software and used to generate SOFT RESET. Other 4
	bits are used to enable interrupt generations.
	5 LSbits in the Interrupt Status register are indicating System Error Int, Parity Error Int, PCI & WB
	Error Int and Inerrupt respecively. System and Parity errors are implented only in HOST bridge
	implementations!
-----------------------------------------------------------------------------------------------------------*/
			reg					icr_bit31 ;
`ifdef		HOST
			reg		[4 : 3]		icr_bit4_3              ;
			reg		[4 : 3]		isr_bit4_3              ;
			reg		[2 : 0]		icr_bit2_0              ;
			reg		[2 : 0]		isr_bit2_0              ;
`else // GUEST
			wire	[4 : 3]		icr_bit4_3 = 2'h0 ;
			wire	[4 : 3]		isr_bit4_3 = 2'h0 ;
			reg		[2 : 0]		icr_bit2_0 ;
			reg		[2 : 0]		isr_bit2_0 ;
`endif

/*###########################################################################################################
-------------------------------------------------------------------------------------------------------------
Initialization complete identifier
    When using I2C or similar initialisation mechanism,
    the bridge must not respond to transaction requests on PCI bus,
    not even to configuration cycles.
    Therefore, only when init_complete is set, the bridge starts
    participating on the PCI bus as an active device.
    Two additional flip flops are also provided for GUEST implementation,
    to synchronize to the pci clock after PCI reset is asynchronously de-asserted.
-------------------------------------------------------------------------------------------------------------
###########################################################################################################*/

`ifdef GUEST

reg rst_inactive_sync ;
reg rst_inactive      ;

`else

wire rst_inactive = 1'b1 ;

`endif

reg init_complete   ;

wire    sync_init_complete ;

`ifdef HOST
assign  wb_init_complete_out = init_complete ;

pci_synchronizer_flop #(1, 0) i_pci_init_complete_sync
(
    .data_in        (   init_complete       ), 
    .clk_out        (   pci_clk             ), 
    .sync_data_out  (   sync_init_complete  ), 
    .async_reset    (   reset               )
);

reg pci_init_complete_out ;

always@(posedge pci_clk or posedge reset)
begin
    if (reset)
        pci_init_complete_out <= 1'b0 ;
    else
        pci_init_complete_out <= sync_init_complete ;
end

`endif

`ifdef GUEST

assign  pci_init_complete_out = init_complete ;

pci_synchronizer_flop #(1, 0) i_wb_init_complete_sync
(
    .data_in        (   init_complete       ), 
    .clk_out        (   wb_clk              ), 
    .sync_data_out  (   sync_init_complete  ), 
    .async_reset    (   reset               )
);

reg wb_init_complete_out ;

always@(posedge wb_clk or posedge reset)
begin
    if (reset)
        wb_init_complete_out <= 1'b0 ;
    else
        wb_init_complete_out <= sync_init_complete ;
end