coregen.log

来自「VHDL写的LMS算法程序。利用本地正弦信号」· LOG 代码 · 共 86 行

# Xilinx CORE Generator 6.2.03i
# User = Chao.SEU
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in F:\FPGA_LMS3\coregen.log
# lockprojectprops=false
# busformat=BusFormatAngleBracketNotRipped
# designflow=VHDL
# expandedprojectpath=F:\FPGA_LMS3
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=Verilog VHDL
# xilinxfamily=Virtex2
# outputoption=OutputProducts
# overwritefiles=true
# simvendor=ModelSim
# expandedprojectpath=F:\FPGA_LMS3
SETPROJECT f:\fpga_lms3
Set current Project to F:\FPGA_LMS3
SET OverwriteFiles=true
LAUNCHXCO costest.xco
SET BusFormat = BusFormatAngleBracketNotRipped
SET XilinxFamily = Virtex2
SET OutputOption = OutputProducts
SET FlowVendor = Foundation_iSE
SET FormalVerification = None
SET OutputProducts = ImpNetlist ASYSymbol VHDLSim VerilogSim
SELECT Sine-Cosine_Look-Up_Table Virtex2 Xilinx,_Inc. 4.2
CSET output_width = 8
CSET handshaking_enabled = false
CSET negative_sine = false
CSET theta_input_width = 6
CSET output_options = Registered
CSET function = Sine
CSET sclr_pin = false
CSET output_symmetry = Symmetric
CSET memory_type = Block_ROM
CSET clock_enable = false
CSET create_rpm = false
CSET negative_cosine = false
CSET pipeline_stages = 1
CSET input_options = Registered
CSET component_name = costest
CSET aclr_pin = true
CSET Input_Options = Registered
CSET ACLR_Pin = true
CSET Function = Sine
CSET Component_Name = costest
CSET Negative_Cosine = false
CSET Memory_Type = Block_ROM
CSET Handshaking_Enabled = true
CSET Clock_Enable = false
CSET Output_Width = 8
CSET Negative_Sine = false
CSET Pipeline_Stages = 1
CSET Theta_Input_Width = 6
CSET Output_Options = Registered
CSET Output_Symmetry = Symmetric
CSET SCLR_Pin = false
CSET Create_RPM = false
GENERATE
Preparing to elaborate core...
Elaborating the module...
Generating the core .EDN implementation netlist...
Generating the .VHO/.VHD simulation support files...
Generating the .VEO/.V simulation support files...
Generating the .ASY symbol file...
Generating ISE symbol file...
# Executing: C:\Xilinx\bin\nt\asy2sym.exe F:\FPGA_LMS3\costest.asy
# Release 6.2i - asy2sym G.28
# Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
# Execution Complete.  Return code: 0
Successfully generated <costest> (Sine-Cosine Look-Up Table 4.2)
 
# busformat=BusFormatAngleBracketNotRipped
# designflow=VHDL
# expandedprojectpath=F:\FPGA_LMS3
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=Verilog VHDL
# xilinxfamily=Virtex2
# outputoption=OutputProducts
# overwritefiles=true
# simvendor=ModelSim
# expandedprojectpath=F:\FPGA_LMS3