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-- Node name is '|LPM_ADD_SUB:56|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC015', type is buried 
_LC015   = LCELL( B3 $  _LC003);

-- Node name is '|LPM_ADD_SUB:57|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC024', type is buried 
_LC024   = LCELL( _EQ008 $  GND);
  _EQ008 = !A0 & !B0 &  _X001 &  _X002
         #  _LC013 &  _LC016 &  _X002
         #  _LC002 &  _LC014;
  _X001  = EXP(!_LC013 & !_LC016);
  _X002  = EXP(!_LC002 & !_LC014);

-- Node name is '|LPM_ADD_SUB:57|addcore:adder|addcore:adder0|g4' from file "addcore.tdf" line 158, column 5
-- Equation name is '_LC018', type is buried 
_LC018   = LCELL( _EQ009 $  _EQ010);
  _EQ009 = !A0 & !B0 &  _X001 &  _X002 &  _X003 &  _X004
         #  _LC013 &  _LC016 &  _X002 &  _X003 &  _X004
         #  _LC002 &  _LC014 &  _X003 &  _X004;
  _X001  = EXP(!_LC013 & !_LC016);
  _X002  = EXP(!_LC002 & !_LC014);
  _X003  = EXP(!_LC015 & !_LC023);
  _X004  = EXP( _LC015 &  _LC023);
  _EQ010 =  _LC015 &  _LC023;

-- Node name is '|LPM_ADD_SUB:57|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC026', type is buried 
_LC026   = LCELL( _EQ011 $  GND);
  _EQ011 = !A0 & !B0 &  _LC013 &  _LC016
         # !A0 & !B0 & !_LC013 & !_LC016
         #  A0 &  _X001 &  _X005
         #  B0 &  _X001 &  _X005;
  _X001  = EXP(!_LC013 & !_LC016);
  _X005  = EXP( _LC013 &  _LC016);

-- Node name is '|LPM_ADD_SUB:57|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC028', type is buried 
_LC028   = LCELL( _EQ012 $  _EQ013);
  _EQ012 = !A0 & !B0 &  _X001
         #  _LC013 &  _LC016;
  _X001  = EXP(!_LC013 & !_LC016);
  _EQ013 =  _X002 &  _X006;
  _X002  = EXP(!_LC002 & !_LC014);
  _X006  = EXP( _LC002 &  _LC014);

-- Node name is '|LPM_ADD_SUB:57|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC030', type is buried 
_LC030   = LCELL( _EQ014 $  _LC024);
  _EQ014 =  _X003 &  _X004;
  _X003  = EXP(!_LC015 & !_LC023);
  _X004  = EXP( _LC015 &  _LC023);

-- Node name is '|LPM_ADD_SUB:64|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC031', type is buried 
_LC031   = LCELL( _EQ015 $  _LC028);
  _EQ015 = !_LC026 &  _LC028 & !SS0;

-- Node name is '|LPM_ADD_SUB:64|addcore:adder|addcore:adder0|g4' from file "addcore.tdf" line 158, column 5
-- Equation name is '_LC027', type is buried 
_LC027   = LCELL( _EQ016 $  GND);
  _EQ016 = !A0 & !B0 &  _LC013 &  _LC016 &  _LC028 &  _LC030
         # !A0 & !B0 & !_LC013 & !_LC016 &  _LC028 &  _LC030
         #  A0 &  _LC028 &  _LC030 &  _X001 &  _X005
         #  B0 &  _LC028 &  _LC030 &  _X001 &  _X005
         #  _LC028 &  _LC030 &  SS0;
  _X001  = EXP(!_LC013 & !_LC016);
  _X005  = EXP( _LC013 &  _LC016);

-- Node name is '|LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC029', type is buried 
_LC029   = LCELL(!_LC028 $  _EQ017);
  _EQ017 = !_LC026 & !SS0;

-- Node name is '|LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC025', type is buried 
_LC025   = LCELL( _LC030 $  _LC031);

-- Node name is '|LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC004', type is buried 
_LC004   = LCELL( _LC018 $  _LC027);

-- Node name is '|LPM_ADD_SUB:70|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC021', type is buried 
_LC021   = LCELL(!_LC028 $  _EQ018);
  _EQ018 =  _LC026 &  SS0;

-- Node name is '|LPM_ADD_SUB:70|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC020', type is buried 
_LC020   = LCELL( _EQ019 $  _LC030);
  _EQ019 = !_LC028 & !SS0
         # !_LC026 & !_LC028;

-- Node name is '|LPM_ADD_SUB:70|addcore:adder|addcore:adder0|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC019', type is buried 
_LC019   = LCELL( _EQ020 $  _LC018);
  _EQ020 = !_LC028 & !_LC030 & !SS0
         # !_LC026 & !_LC028 & !_LC030;

-- Node name is '|LPM_ADD_SUB:107|addcore:adder|addcore:adder0|gs2' from file "addcore.tdf" line 148, column 7
-- Equation name is '_LC001', type is buried 
_LC001   = LCELL( _EQ021 $  GND);
  _EQ021 =  _LC018 &  _LC029
         # !_LC018 &  _LC021;

-- Node name is '|LPM_ADD_SUB:107|addcore:adder|addcore:adder0|gs3' from file "addcore.tdf" line 148, column 7
-- Equation name is '_LC005', type is buried 
_LC005   = LCELL( _EQ022 $  GND);
  _EQ022 =  _LC018 &  _LC025
         # !_LC018 &  _LC020;

-- Node name is '|LPM_ADD_SUB:107|addcore:adder|addcore:adder0|gs4' from file "addcore.tdf" line 148, column 7
-- Equation name is '_LC006', type is buried 
_LC006   = LCELL( _EQ023 $  GND);
  _EQ023 =  _LC004 &  _LC018
         # !_LC018 &  _LC019;

-- Node name is '|LPM_ADD_SUB:107|addcore:adder|addcore:adder0|g4' from file "addcore.tdf" line 158, column 5
-- Equation name is '_LC007', type is buried 
_LC007   = LCELL( _EQ024 $  GND);
  _EQ024 = !_LC005 &  _LC018 & !_LC025 &  _LC029
         # !_LC005 & !_LC018 & !_LC020 &  _LC021
         #  _LC018 &  _LC025 &  _X007
         # !_LC018 &  _LC020 &  _X008;
  _X007  = EXP(!_LC005 &  _LC029);
  _X008  = EXP(!_LC005 &  _LC021);

-- Node name is '|LPM_ADD_SUB:107|addcore:adder|addcore:adder0|ps1' from file "addcore.tdf" line 150, column 7
-- Equation name is '_LC022', type is buried 
_LC022   = LCELL( _EQ025 $  _LC026);
  _EQ025 =  _LC018 &  SS0
         # !_LC018 & !SS0;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                              d:\add\ad.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,936K

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