📄 ad.rpt
字号:
r = Fitter-inserted logic cell
Device-Specific Information: d:\add\ad.rpt
ad
** BURIED LOGIC **
Shareable
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Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(12) 8 A SOFT t 0 0 0 3 0 0 1 |LPM_ADD_SUB:51|addcore:adder|addcore:adder0|gcp2
(21) 16 A SOFT t 0 0 0 2 0 0 5 |LPM_ADD_SUB:51|addcore:adder|addcore:adder0|result_node1
(5) 2 A SOFT t 0 0 0 3 0 0 3 |LPM_ADD_SUB:51|addcore:adder|addcore:adder0|result_node2
(34) 23 B SOFT t 0 0 0 1 1 0 2 |LPM_ADD_SUB:51|addcore:adder|addcore:adder0|result_node3
(6) 3 A SOFT t 0 0 0 3 0 0 1 |LPM_ADD_SUB:56|addcore:adder|addcore:adder0|gcp2
(18) 13 A SOFT t 0 0 0 2 0 0 5 |LPM_ADD_SUB:56|addcore:adder|addcore:adder0|result_node1
(19) 14 A SOFT t 0 0 0 3 0 0 3 |LPM_ADD_SUB:56|addcore:adder|addcore:adder0|result_node2
(20) 15 A SOFT t 0 0 0 1 1 0 2 |LPM_ADD_SUB:56|addcore:adder|addcore:adder0|result_node3
(33) 24 B SOFT t 2 2 0 2 4 0 1 |LPM_ADD_SUB:57|addcore:adder|addcore:adder0|gcp2
(40) 18 B SOFT t 4 4 0 2 6 2 7 |LPM_ADD_SUB:57|addcore:adder|addcore:adder0|g4
(31) 26 B SOFT t 2 2 0 2 2 0 6 |LPM_ADD_SUB:57|addcore:adder|addcore:adder0|result_node1
(28) 28 B SOFT t 3 2 0 2 4 0 6 |LPM_ADD_SUB:57|addcore:adder|addcore:adder0|result_node2
(26) 30 B SOFT t 2 2 0 0 3 0 4 |LPM_ADD_SUB:57|addcore:adder|addcore:adder0|result_node3
(25) 31 B SOFT t 0 0 0 0 3 0 1 |LPM_ADD_SUB:64|addcore:adder|addcore:adder0|gcp2
(29) 27 B SOFT t 3 2 1 2 5 0 1 |LPM_ADD_SUB:64|addcore:adder|addcore:adder0|g4
(27) 29 B SOFT t 0 0 0 0 3 2 2 |LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node2
(32) 25 B SOFT t 0 0 0 0 2 0 2 |LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node3
(7) 4 A SOFT t 0 0 0 0 2 0 1 |LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node4
(37) 21 B SOFT t 0 0 0 0 3 2 2 |LPM_ADD_SUB:70|addcore:adder|addcore:adder0|result_node2
(38) 20 B SOFT t 0 0 0 0 4 0 2 |LPM_ADD_SUB:70|addcore:adder|addcore:adder0|result_node3
(39) 19 B SOFT t 0 0 0 0 5 0 1 |LPM_ADD_SUB:70|addcore:adder|addcore:adder0|result_node4
(4) 1 A SOFT t 0 0 0 0 3 1 0 |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|gs2
(8) 5 A SOFT t 0 0 0 0 3 1 1 |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|gs3
(9) 6 A SOFT t 0 0 0 0 3 1 0 |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|gs4
(11) 7 A SOFT t 2 0 0 0 6 1 0 |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|g4
(36) 22 B SOFT t 0 0 0 0 3 4 0 |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|ps1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\add\ad.rpt
ad
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------------------------------- LC8 |LPM_ADD_SUB:51|addcore:adder|addcore:adder0|gcp2
| +----------------------------- LC16 |LPM_ADD_SUB:51|addcore:adder|addcore:adder0|result_node1
| | +--------------------------- LC2 |LPM_ADD_SUB:51|addcore:adder|addcore:adder0|result_node2
| | | +------------------------- LC3 |LPM_ADD_SUB:56|addcore:adder|addcore:adder0|gcp2
| | | | +----------------------- LC13 |LPM_ADD_SUB:56|addcore:adder|addcore:adder0|result_node1
| | | | | +--------------------- LC14 |LPM_ADD_SUB:56|addcore:adder|addcore:adder0|result_node2
| | | | | | +------------------- LC15 |LPM_ADD_SUB:56|addcore:adder|addcore:adder0|result_node3
| | | | | | | +----------------- LC4 |LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node4
| | | | | | | | +--------------- LC1 |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|gs2
| | | | | | | | | +------------- LC5 |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|gs3
| | | | | | | | | | +----------- LC6 |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|gs4
| | | | | | | | | | | +--------- LC7 |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|g4
| | | | | | | | | | | | +------- LC9 SS1
| | | | | | | | | | | | | +----- LC10 SS2
| | | | | | | | | | | | | | +--- LC11 SS3
| | | | | | | | | | | | | | | +- LC12 SS4
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'A':
LC3 -> - - - - - - * - - - - - - - - - | * - | <-- |LPM_ADD_SUB:56|addcore:adder|addcore:adder0|gcp2
LC4 -> - - - - - - - - - - * - - - - - | * - | <-- |LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node4
LC1 -> - - - - - - - - - - - - - * - - | * - | <-- |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|gs2
LC5 -> - - - - - - - - - - - * - - * - | * - | <-- |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|gs3
LC6 -> - - - - - - - - - - - - - - - * | * - | <-- |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|gs4
LC7 -> - - - - - - - - - - - - - - - * | * - | <-- |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|g4
Pin
4 -> * * * - - - - - - - - - - - - - | * * | <-- A0
12 -> * * * - - - - - - - - - - - - - | * - | <-- A1
11 -> * - * - - - - - - - - - - - - - | * - | <-- A2
5 -> - - - * * * - - - - - - - - - - | * * | <-- B0
8 -> - - - * * * - - - - - - - - - - | * - | <-- B1
7 -> - - - * - * - - - - - - - - - - | * - | <-- B2
6 -> - - - - - - * - - - - - - - - - | * - | <-- B3
LC18 -> - - - - - - - * * * * * - * * - | * * | <-- |LPM_ADD_SUB:57|addcore:adder|addcore:adder0|g4
LC27 -> - - - - - - - * - - - - - - - - | * - | <-- |LPM_ADD_SUB:64|addcore:adder|addcore:adder0|g4
LC29 -> - - - - - - - - * - - * - * * - | * - | <-- |LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node2
LC25 -> - - - - - - - - - * - * - - - - | * - | <-- |LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node3
LC21 -> - - - - - - - - * - - * - * * - | * - | <-- |LPM_ADD_SUB:70|addcore:adder|addcore:adder0|result_node2
LC20 -> - - - - - - - - - * - * - - - - | * - | <-- |LPM_ADD_SUB:70|addcore:adder|addcore:adder0|result_node3
LC19 -> - - - - - - - - - - * - - - - - | * - | <-- |LPM_ADD_SUB:70|addcore:adder|addcore:adder0|result_node4
LC22 -> - - - - - - - - - - - - * * * * | * - | <-- |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|ps1
LC17 -> - - - - - - - - - - - - * * * * | * * | <-- SS0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\add\ad.rpt
ad
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----------------------------- LC23 |LPM_ADD_SUB:51|addcore:adder|addcore:adder0|result_node3
| +--------------------------- LC24 |LPM_ADD_SUB:57|addcore:adder|addcore:adder0|gcp2
| | +------------------------- LC18 |LPM_ADD_SUB:57|addcore:adder|addcore:adder0|g4
| | | +----------------------- LC26 |LPM_ADD_SUB:57|addcore:adder|addcore:adder0|result_node1
| | | | +--------------------- LC28 |LPM_ADD_SUB:57|addcore:adder|addcore:adder0|result_node2
| | | | | +------------------- LC30 |LPM_ADD_SUB:57|addcore:adder|addcore:adder0|result_node3
| | | | | | +----------------- LC31 |LPM_ADD_SUB:64|addcore:adder|addcore:adder0|gcp2
| | | | | | | +--------------- LC27 |LPM_ADD_SUB:64|addcore:adder|addcore:adder0|g4
| | | | | | | | +------------- LC29 |LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node2
| | | | | | | | | +----------- LC25 |LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node3
| | | | | | | | | | +--------- LC21 |LPM_ADD_SUB:70|addcore:adder|addcore:adder0|result_node2
| | | | | | | | | | | +------- LC20 |LPM_ADD_SUB:70|addcore:adder|addcore:adder0|result_node3
| | | | | | | | | | | | +----- LC19 |LPM_ADD_SUB:70|addcore:adder|addcore:adder0|result_node4
| | | | | | | | | | | | | +--- LC22 |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|ps1
| | | | | | | | | | | | | | +- LC17 SS0
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC23 -> - - * - - * - - - - - - - - - | - * | <-- |LPM_ADD_SUB:51|addcore:adder|addcore:adder0|result_node3
LC24 -> - - - - - * - - - - - - - - - | - * | <-- |LPM_ADD_SUB:57|addcore:adder|addcore:adder0|gcp2
LC18 -> - - - - - - - - - - - - * * - | * * | <-- |LPM_ADD_SUB:57|addcore:adder|addcore:adder0|g4
LC26 -> - - - - - - * - * - * * * * - | - * | <-- |LPM_ADD_SUB:57|addcore:adder|addcore:adder0|result_node1
LC28 -> - - - - - - * * * - * * * - - | - * | <-- |LPM_ADD_SUB:57|addcore:adder|addcore:adder0|result_node2
LC30 -> - - - - - - - * - * - * * - - | - * | <-- |LPM_ADD_SUB:57|addcore:adder|addcore:adder0|result_node3
LC31 -> - - - - - - - - - * - - - - - | - * | <-- |LPM_ADD_SUB:64|addcore:adder|addcore:adder0|gcp2
LC17 -> - - - - - - * * * - * * * * - | * * | <-- SS0
Pin
4 -> - * * * * - - * - - - - - - * | * * | <-- A0
9 -> * - - - - - - - - - - - - - - | - * | <-- A3
5 -> - * * * * - - * - - - - - - * | * * | <-- B0
LC8 -> * - - - - - - - - - - - - - - | - * | <-- |LPM_ADD_SUB:51|addcore:adder|addcore:adder0|gcp2
LC16 -> - * * * * - - * - - - - - - - | - * | <-- |LPM_ADD_SUB:51|addcore:adder|addcore:adder0|result_node1
LC2 -> - * * - * - - - - - - - - - - | - * | <-- |LPM_ADD_SUB:51|addcore:adder|addcore:adder0|result_node2
LC13 -> - * * * * - - * - - - - - - - | - * | <-- |LPM_ADD_SUB:56|addcore:adder|addcore:adder0|result_node1
LC14 -> - * * - * - - - - - - - - - - | - * | <-- |LPM_ADD_SUB:56|addcore:adder|addcore:adder0|result_node2
LC15 -> - - * - - * - - - - - - - - - | - * | <-- |LPM_ADD_SUB:56|addcore:adder|addcore:adder0|result_node3
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\add\ad.rpt
ad
** EQUATIONS **
A0 : INPUT;
A1 : INPUT;
A2 : INPUT;
A3 : INPUT;
B0 : INPUT;
B1 : INPUT;
B2 : INPUT;
B3 : INPUT;
-- Node name is 'SS0'
-- Equation name is 'SS0', location is LC017, type is output.
SS0 = LCELL(!B0 $ !A0);
-- Node name is 'SS1'
-- Equation name is 'SS1', location is LC009, type is output.
SS1 = LCELL(!_LC022 $ !SS0);
-- Node name is 'SS2'
-- Equation name is 'SS2', location is LC010, type is output.
SS2 = LCELL( _EQ001 $ GND);
_EQ001 = _LC018 & !_LC022 & _LC029 & !SS0
# !_LC018 & _LC021 & !_LC022 & !SS0
# !_LC001 & _LC022
# !_LC001 & SS0;
-- Node name is 'SS3'
-- Equation name is 'SS3', location is LC011, type is output.
SS3 = LCELL( _EQ002 $ !_LC005);
_EQ002 = _LC018 & _LC029
# !_LC018 & _LC021
# !_LC022 & !SS0;
-- Node name is 'SS4'
-- Equation name is 'SS4', location is LC012, type is output.
SS4 = LCELL( _EQ003 $ !_LC006);
_EQ003 = !_LC022 & !SS0
# _LC007;
-- Node name is '|LPM_ADD_SUB:51|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC008', type is buried
_LC008 = LCELL( _EQ004 $ A2);
_EQ004 = !A0 & !A1 & A2;
-- Node name is '|LPM_ADD_SUB:51|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC016', type is buried
_LC016 = LCELL(!A1 $ A0);
-- Node name is '|LPM_ADD_SUB:51|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC002', type is buried
_LC002 = LCELL(!A2 $ _EQ005);
_EQ005 = !A0 & !A1;
-- Node name is '|LPM_ADD_SUB:51|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC023', type is buried
_LC023 = LCELL( A3 $ _LC008);
-- Node name is '|LPM_ADD_SUB:56|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC003', type is buried
_LC003 = LCELL( _EQ006 $ B2);
_EQ006 = !B0 & !B1 & B2;
-- Node name is '|LPM_ADD_SUB:56|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC013', type is buried
_LC013 = LCELL(!B1 $ B0);
-- Node name is '|LPM_ADD_SUB:56|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC014', type is buried
_LC014 = LCELL(!B2 $ _EQ007);
_EQ007 = !B0 & !B1;
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