fdpll.vhd

简单的可配置dpll的VHDL代码。 用于时钟恢复后的相位抖动的滤波有很好的效果

--**********************************************************************************
--     Title   : CM218 receiver baseband design
--     Project : RxTOP
--     File    : dpll.vhd
--     Author  : Sam Chan([e-mail])
--     Company : Concord Electronics
--     Created : May. 18th., 2005
--     Platform     : QuartusII5.1  
--     Simulators   : Modelsim SE 5.8c
--     Synthesizers : Synplify Pro 7.6
--     Target       : EPM240T100C5
--***********************************************************************************
--
--     Revision	    : Rev2
--     Date         : 2005.12.22
--     Modification : 
--      1. Output clock use the clock enable form because of MAXII's LUT structure
--      2. Change the phase locked area, to release the skew of the out put clocks 
--         for DAC  
--      3. Use the two level of the phase lock loop to smooth the clock 
--**********************************************************************************


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.all;


ENTITY dpll IS
generic
(
  DATA_WIDTH : integer := 2 ; -- The parameter data width
  SKEW       : integer := 2 
);
PORT 
(
-- In ports
  rclk   : in  std_logic ; -- The refence clock input 
  rstp   : in  std_logic ; -- Dpll reset
  clkin  : in  std_logic ; -- The adjusting clock input
  datai  : in  std_logic_vector(DATA_WIDTH - 1 downto 0) ; -- The data bus input
-- Out ports
  datao  : out std_logic_vector(DATA_WIDTH - 1 downto 0) ; -- The data bus output
  clko   : out std_logic   -- The pll clock output
);
END dpll;

ARCHITECTURE RTL OF dpll IS

constant SKEW_VEC   : std_logic_vector(4 downto 0) := CONV_STD_LOGIC_VECTOR(SKEW, 5) ;  
constant AHEAD_MODE : std_logic_vector(4 downto 0) := "10000" ;
constant LAG_MODE   : std_logic_vector(4 downto 0) := "01110" ;
constant EQU_MODE   : std_logic_vector(4 downto 0) := "01111" ; 
 
SIGNAL dpllcnt   : std_logic_vector(4 downto 0) ;
SIGNAL varmode   : std_logic_vector(4 downto 0) ;

attribute syn_preserve : boolean ;
attribute syn_preserve of varmode : signal is true ;

BEGIN

  -------------------------------------------------------
  data_dff :
  -------------------------------------------------------
  process(rclk, rstp)
  begin
  if rstp = '1' then
     datao <= (others => '0') ;
  else
    if rclk'event and rclk = '1' then
  -------------------------------------------------------
  -- Synchronize the input data or other bits
  -------------------------------------------------------
       datao <= datai ;
    end if;
  end if;
  end process ;  

  -------------------------------------------------------
  edge_phase_detector :
  -------------------------------------------------------
  process(rclk, rstp)
  begin
  if rstp = '1' then	
     varmode <= "01111" ;
  else
    if rclk'event and rclk = '1'  then
      if clkin = '1' then
        if    dpllcnt < "01000" - SKEW_VEC then  
  ------------------------------------------------------  
   --      Phase error : ahead
  ------------------------------------------------------
           varmode <= AHEAD_MODE ;
        elsif dpllcnt > "01000" + SKEW_VEC then 
  ------------------------------------------------------
  --       Phase error : lag
  ------------------------------------------------------
           varmode <= LAG_MODE ;
        else
  ------------------------------------------------------
  --       Phase error : Equal
  ------------------------------------------------------
           varmode <= EQU_MODE ;
        end if;
      end if;
    end if;
  end if;
  end process ;

  ------------------------------------------------------
  var_mode_counter :
  ------------------------------------------------------
  process(rclk,rstp)
  begin
  if rstp = '1' then
     dpllcnt <= ( others => '0') ;
  else
    if rclk'event and rclk = '1' then
      if dpllcnt = "00000" then
  ------------------------------------------------------
  --   Change the mode of the counter 
  ------------------------------------------------------
         dpllcnt <= varmode ; 
      else
         dpllcnt <= dpllcnt - 1 ;
      end if;
    end if;
  end if;
  end process;

  -------------------------------------------------------
  clk_enable :
  -------------------------------------------------------
    clko <= '1' when  dpllcnt = "00000" else '0' ;
  -------------------------------------------------------
	
END RTL;



LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.all;

entity ddpll is -- Double dpll 
generic
(
  DATA_WIDTH : integer := 2 ;
  PLL_AMOUNT : integer := 2 
);
port
(
-- In ports
  rclk  : in  std_logic ; -- Reference clock input
  clkin : in  std_logic ; -- Input clock
  rstp  : in  std_logic ; 
  datai : in  std_logic_vector(DATA_WIDTH - 1 downto 0) ; -- The data bus input
-- Out ports  
  datao : out std_logic_vector(DATA_WIDTH - 1 downto 0) ; -- The data bus output
  clko  : out std_logic   -- Clock output
);
end ddpll;

architecture RTL of ddpll is

component dpll 
generic
( DATA_WIDTH : integer := 2;
  SKEW       : integer := 2
);
port
(
  rclk  : in  std_logic ; 
  rstp  : in  std_logic ; 
  clkin : in  std_logic ;
  datai : in  std_logic_vector(DATA_WIDTH - 1 downto 0) ;
  datao : out std_logic_vector(DATA_WIDTH - 1 downto 0) ; 
  clko  : out std_logic   
);
end component;

type data_arry is array(PLL_AMOUNT downto 0) of std_logic_vector(DATA_WIDTH - 1 downto 0) ;

signal clk_i  : std_logic_vector(PLL_AMOUNT downto 0) ;
signal data_i : data_arry ; 

begin
  
  ---------------------------------------------
  clock_enable_in :
  ---------------------------------------------
    clk_i(0) <= clkin ;
  
  ---------------------------------------------
  data_in :
  ---------------------------------------------
    data_i(0) <= datai ;
  

  ---------------------------------------------
  clock_enable_out :
  ---------------------------------------------
    clko  <= clk_i(PLL_AMOUNT) ;
  
  ---------------------------------------------
  data_out :
  ---------------------------------------------
    datao <= data_i(PLL_AMOUNT) ; 

  ---------------------------------------------
  plls_gen :
  ---------------------------------------------
  for i in 0 to PLL_AMOUNT - 1 
  generate
    pll_type : dpll
    generic map
    (
      DATA_WIDTH => DATA_WIDTH ,
      SKEW       => 2
    )
    port    map
    (
      rclk  => rclk ,
      rstp  => rstp ,
      clkin => clk_i(i) ,
      datai => data_i(i) ,
      datao => data_i(i + 1) ,
      clko  => clk_i (i + 1) 
     );
   end generate;
  
end RTL;