spi_map.v

verilog语言写的SPI接口,全同步设计,低门数,可以很容易应用到嵌入设计方案中.

//dummy coment to make synopsys work
//synopsys translate_off
`ifdef __SPI_MAP__V_INCLUDED    
`else                       
`define __SPI_MAP__V_INCLUDED 
//synopsys translate_on  
`define OPCODE_MSB  8'h00
`define OPCODE_02   8'h01
`define OPCODE_01   8'h02
`define OPCODE_LSB  8'h03

`define ADDRESS_MSB 8'h04
`define ADDRESS_02  8'h05
`define ADDRESS_01  8'h06
`define ADDRESS_LSB 8'h07

`define TxRx_FIFO   8'h08

`define START_BUSY  8'h09

`define OPCODE_SIZE 8'h0a
`define ADDR_SIZE   8'h0b

`define DEVICE_CTRL 8'h0c
`define SPI_CK_CTRL 8'h0d
`define SPI_CS_CTRL 8'h0e

`define MISC_CTRL   8'h0f

`define IT_STATUS   8'h10
`define IT_MASK     8'h11

`define TRIGGER     8'h12

`define PAGE_SIZE   8'h13
`define FIFO_STATUS 8'h14

`define NB_TRANSMIT 8'h15




// synopsys translate_off
`endif
// synopsys translate_on