pipemult_lc_phys_syn.fit.rpt

来自「使用Quartus II 5.0开发指导手册」· RPT 代码 · 共 478 行 · 第 1/5 页

Fitter report for pipemult_lc_phys_syn
Fri May 27 17:08:13 2005
Version 5.0 Build 148 04/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Device Options
  5. Fitter Netlist Optimizations
  6. Fitter Equations
  7. HardCopy II Device Resource Guide
  8. Pin-Out File
  9. Fitter Resource Usage Summary
 10. Input Pins
 11. Output Pins
 12. I/O Bank Usage
 13. All Package Pins
 14. Output Pin Default Load For Reported TCO
 15. Fitter Resource Utilization by Entity
 16. Delay Chain Summary
 17. Pad To Core Delay Chain Fanout
 18. Control Signals
 19. Global & Other Fast Signals
 20. Non-Global High Fan-Out Signals
 21. Fitter RAM Summary
 22. Interconnect Usage Summary
 23. LAB Logic Elements
 24. LAB-wide Signals
 25. LAB Signals Sourced
 26. LAB Signals Sourced Out
 27. LAB Distinct Inputs
 28. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+---------------------------------------------------------------------+
; Fitter Summary                                                      ;
+--------------------------+------------------------------------------+
; Fitter Status            ; Successful - Fri May 27 17:08:13 2005    ;
; Quartus II Version       ; 5.0 Build 148 04/26/2005 SJ Full Version ;
; Revision Name            ; pipemult_lc_phys_syn                     ;
; Top-level Entity Name    ; pipemult                                 ;
; Family                   ; Stratix II                               ;
; Device                   ; EP2S15F484C3                             ;
; Timing Models            ; Preliminary                              ;
; Total ALUTs              ; 86 / 12,480 ( < 1 % )                    ;
; Total pins               ; 44 / 343 ( 12 % )                        ;
; Total virtual pins       ; 0                                        ;
; Total memory bits        ; 512 / 419,328 ( < 1 % )                  ;
; DSP block 9-bit elements ; 0 / 96 ( 0 % )                           ;
; Total PLLs               ; 0 / 6 ( 0 % )                            ;
; Total DLLs               ; 0 / 2 ( 0 % )                            ;
+--------------------------+------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                      ;
+----------------------------------------------------+--------------------------------+--------------------------------+
; Option                                             ; Setting                        ; Default Value                  ;
+----------------------------------------------------+--------------------------------+--------------------------------+
; Device                                             ; EP2S15F484C3                   ;                                ;
; Perform Register Retiming                          ; On                             ; Off                            ;
; Use smart compilation                              ; Off                            ; Off                            ;
; Placement Effort Multiplier                        ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                           ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                        ; Off                            ; Off                            ;
; Optimize Timing                                    ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing         ; On                             ; On                             ;
; Limit to One Fitting Attempt                       ; Off                            ; Off                            ;
; Final Placement Optimizations                      ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                      ; 1                              ; 1                              ;
; PCI I/O                                            ; Off                            ; Off                            ;