pipemult_lc_phys_syn.fit.rpt
来自「使用Quartus II 5.0开发指导手册」· RPT 代码 · 共 478 行 · 第 1/5 页
RPT
478 行
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[13]~191 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[8]~193 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add12_result[2]~40 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[8]~194 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[8]~194 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[9]~196 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add12_result[3]~41 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[9]~197 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[9]~197 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[10]~199 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add12_result[4]~42 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[10]~200 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[10]~200 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ;
+-------------------------------------------------------------------------------------------------------------------------------------------------+------------------+--------------------+---------------------+-----------+------------------+------------------+
+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/pipemult_lc_phys_syn.fit.eqn.
Color Legend:
-- Green:
-- Package Resource: The HardCopy II package can be migrated from the Stratix II FPGA selected package, and the design has been fitted with the target device migration enabled.
-- Other Device Resources: The resource quantity is within the acceptable range in the HardCopy II device and package, and will likely migrate from the Stratix II FPGA selected package.
-- Orange:
-- Package Resource: The HardCopy II package can be migrated from the Stratix II FPGA selected package; however, the design has not been fitted with the target device migration enabled.
-- Other Device Resources: The resource quantity is within the acceptable range in the HardCopy II device and package; however, the resource is constrained so much that the design may not migrate.
-- Red:
-- Package Resource: The HardCopy II package cannot be migrated from the Stratix II FPGA selected package.
-- Other Device Resources: The design did not migrate because the resource quantity exceeds the acceptable range in the HardCopy II device and package, or, for other reasons detailed in the footnotes.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; HardCopy II Device Resource Guide ;
+------------------------------------+----------------------+--------------+--------------+--------------+--------------+---------------+---------------+---------------+
; Resource ; Stratix II EP2S15 ; HC210W* ; HC210 ; HC220 ; HC220 ; HC230 ; HC240 ; HC240 ;
+------------------------------------+----------------------+--------------+--------------+--------------+--------------+---------------+---------------+---------------+
; Migration Compatibility ; ; ; None ; None ; None ; None ; None ; None ;
; Primary Migration Constraint ; ; ; Package ; Package ; Package ; Package ; Package ; Package ;
; Package** ; FBGA - 484 ; FBGA - 484 ; FBGA - 484 ; FBGA - 672 ; FBGA - 780 ; FBGA - 1020 ; FBGA - 1020 ; FBGA - 1508 ;
; Logic ; -- ; ; 1% ; 1% ; 1% ; 1% ; 1% ; 1% ;
; -- Logic cells ; 86 ALUTs ; ; -- ; -- ; -- ; -- ; -- ; -- ;
; -- DSP elements ; 0 ; ; -- ; -- ; -- ; -- ; -- ; -- ;
; Pins ; ; ; ; ; ; ; ; ;
; -- Total ; 44 ; ; 44 / 335 ; 44 / 493 ; 44 / 495 ; 44 / 699 ; 44 / 743 ; 44 / 952 ;
; -- Differential Input ; 0 ; ; 0 / 70 ; 0 / 90 ; 0 / 90 ; 0 / 128 ; 0 / 224 ; 0 / 272 ;
; -- Differential Output ; 0 ; ; 0 / 50 ; 0 / 70 ; 0 / 70 ; 0 / 112 ; 0 / 200 ; 0 / 256 ;
; -- PCI / PCI-X ; 0 ; ; 0 / 167 ; 0 / 245 ; 0 / 247 ; 0 / 359 ; 0 / 367 ; 0 / 472 ;
; -- DQ ; 0 ; ; 0 / 18 ; 0 / 44 ; 0 / 44 ; 0 / 178 ; 0 / 178 ; 0 / 178 ;
; -- DQS ; 0 ; ; 0 / 8 ; 0 / 18 ; 0 / 18 ; 0 / 72 ; 0 / 72 ; 0 / 72 ;
; Memory ; ; ; ; ; ; ; ; ;
; -- M-RAM ; 0 ; ; 0 / 0 ; 0 / 2 ; 0 / 2 ; 0 / 6 ; 0 / 9 ; 0 / 9 ;
; -- M4K blocks & M512 blocks*** ; 1 ; ; 1 / 190 ; 1 / 408 ; 1 / 408 ; 1 / 614 ; 1 / 816 ; 1 / 816 ;
; PLLs ; ; ; ; ; ; ; ; ;
; -- Enhanced ; 0 ; ; 0 / 2 ; 0 / 2 ; 0 / 2 ; 0 / 4 ; 0 / 4 ; 0 / 4 ;
; -- Fast ; 0 ; ; 0 / 2 ; 0 / 2 ; 0 / 2 ; 0 / 4 ; 0 / 8 ; 0 / 8 ;
; DLLs ; 0 ; ; 0 / 1 ; 0 / 1 ; 0 / 1 ; 0 / 2 ; 0 / 2 ; 0 / 2 ;
; SERDES ; ; ; ; ; ; ; ; ;
; -- RX ; 0 ; ; 0 / 21 ; 0 / 31 ; 0 / 31 ; 0 / 46 ; 0 / 92 ; 0 / 116 ;
; -- TX ; 0 ; ; 0 / 19 ; 0 / 29 ; 0 / 29 ; 0 / 44 ; 0 / 88 ; 0 / 116 ;
; Configuration ; ; ; ; ; ; ; ; ;
; -- CRC ; 0 ; ; 0 / 0 ; 0 / 0 ; 0 / 0 ; 0 / 0 ; 0 / 0 ; 0 / 0 ;
; -- ASMI ; 0 ; ; 0 / 0 ; 0 / 0 ; 0 / 0 ; 0 / 0 ; 0 / 0 ; 0 / 0 ;
; -- Remote Update ; 0 ; ; 0 / 0 ; 0 / 0 ; 0 / 0 ; 0 / 0 ; 0 / 0 ; 0 / 0 ;
; -- JTAG ; 0 ; ; 0 / 1 ; 0 / 1 ; 0 / 1 ; 0 / 1 ; 0 / 1 ; 0 / 1 ;
+------------------------------------+----------------------+--------------+--------------+--------------+--------------+---------------+---------------+---------------+
* Device is preliminary. Overall performance is expected to be degraded.
** The selected Stratix II FPGA device cannot migrate to any HardCopy II device, regardless of the design. Try this design with a different Stratix II FPGA device.
*** Design contains one or more M512 blocks, which cannot be migrated to HardCopy II devices.
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/pipemult_lc_phys_syn.pin.
+--------------------------------------------------------------------------+
; Fitter Resource Usage Summary ;
+------------------------------------------------+-------------------------+
; Resource ; Usage ;
+------------------------------------------------+-------------------------+
; Total ALUTs ; 86 / 12,480 ( < 1 % ) ;
; -- ALUTs Used ; 86 ;
; -- Combinational with no register ; 27 ;
; -- Register only ; 12 ;
; -- Combinational with a register ; 47 ;
; -- ALUTs Unavailable ; 0 ;
; -- Due to unpartnered 7 input function ; 0 ;
; -- Due to unpartnered 6 input function ; 0 ;
; ; ;
; ALUT usage by number of inputs ; ;
; -- 7 input functions ; 0 ;
; -- 6 input functions ; 0 ;
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