pipemult_lc_phys_syn.fit.rpt

来自「使用Quartus II 5.0开发指导手册」· RPT 代码 · 共 478 行 · 第 1/5 页

; Weak Pull-Up Resistor                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                          ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                 ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/Cyclone II     ; Auto                           ; Auto                           ;
; Auto Delay Chains                                  ; On                             ; On                             ;
; Auto Merge PLLs                                    ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic ; Off                            ; Off                            ;
; Perform Register Duplication                       ; Off                            ; Off                            ;
; Fitter Effort                                      ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                    ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication           ; Auto                           ; Auto                           ;
; Auto Register Duplication                          ; Off                            ; Off                            ;
; Auto Global Clock                                  ; On                             ; On                             ;
; Auto Global Register Control Signals               ; On                             ; On                             ;
+----------------------------------------------------+--------------------------------+--------------------------------+


+-------------------------------------------------------------------------+
; Fitter Device Options                                                   ;
+----------------------------------------------+--------------------------+
; Option                                       ; Setting                  ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Configuration scheme                         ; Passive Serial           ;
; Error detection CRC                          ; Off                      ;
; Reserve Data[0] pin after configuration      ; As input tri-stated      ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Netlist Optimizations                                                                                                                                                                                                                                    ;
+-------------------------------------------------------------------------------------------------------------------------------------------------+------------------+--------------------+---------------------+-----------+------------------+------------------+
; Node                                                                                                                                            ; Action           ; Operation          ; Reason              ; Node Port ; Destination Node ; Destination Port ;
+-------------------------------------------------------------------------------------------------------------------------------------------------+------------------+--------------------+---------------------+-----------+------------------+------------------+
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[11]~125 ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[12]~127 ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[7]~137  ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[15]                                              ; Deleted          ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[14]                                              ; Deleted          ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[13]                                              ; Deleted          ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[12]                                              ; Deleted          ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[11]                                              ; Deleted          ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[10]                                              ; Deleted          ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[9]                                               ; Deleted          ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[8]                                               ; Deleted          ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[7]                                               ; Deleted          ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[6]                                               ; Deleted          ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[5]                                               ; Deleted          ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[4]                                               ; Deleted          ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[3]                                               ; Deleted          ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[2]                                               ; Deleted          ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[8]~101  ; Modified         ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[9]~105  ; Modified         ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[10]~109 ; Modified         ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[11]~113 ; Modified         ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[13]~121 ; Modified         ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[3]~129  ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[4]~131  ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[5]~133  ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[6]~135  ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[2]~155  ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[8]~139  ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[9]~141  ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[10]~143 ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[12]~145 ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[9]~147  ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[10]~149 ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[11]~151 ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[1]~153  ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[5]~175  ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[3]~157  ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[4]~159  ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[5]~161  ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[7]~163  ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[0]~165  ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[1]~167  ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[2]~169  ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[3]~171  ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[4]~173  ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add7_result[9]~89   ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[6]~177  ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[6]~179  ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[7]~181  ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[2]~183  ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[0]~185  ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[11]~187 ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add7_result[7]~88   ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[11]~188 ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[11]~188 ; Deleted          ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[13]~190 ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;
; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|add2_result[13]~191 ; Retimed Register ; Physical Synthesis ; Timing optimization ;           ;                  ;                  ;