_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity trig_table is
    generic(
        theta_width     : integer := 10;
        output_width    : integer := 8;
        pi              : real    := 3.141593
    );
    port(
        theta           : in     vl_logic_vector;
        sin_table       : out    vl_logic_vector;
        cos_table       : out    vl_logic_vector
    );
end trig_table;