_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity lfsr_v2_0 is
    generic(
        c_ainit_val     : string  := "11111111";
        c_enable_rlocs  : integer := 0;
        c_gate          : integer := 0;
        c_has_ainit     : integer := 0;
        c_has_ce        : integer := 0;
        c_has_data_valid: integer := 0;
        c_has_load      : integer := 0;
        c_has_load_taps : integer := 0;
        c_has_new_seed  : integer := 0;
        c_has_pd_in     : integer := 0;
        c_has_pd_out    : integer := 0;
        c_has_sd_in     : integer := 0;
        c_has_sd_out    : integer := 1;
        c_has_sinit     : integer := 0;
        c_has_taps_in   : integer := 0;
        c_has_term_cnt  : integer := 0;
        c_implementation: integer := 0;
        c_max_len_logic : integer := 0;
        c_max_len_logic_type: integer := 0;
        c_sinit_val     : string  := "11111111";
        c_size          : integer := 8;
        c_tap_pos       : string  := "00011101";
        c_type          : integer := 0;
        yes             : integer := 1;
        no              : integer := 0
    );
    port(
        clk             : in     vl_logic;
        sd_out          : out    vl_logic;
        pd_out          : out    vl_logic_vector;
        load            : in     vl_logic;
        pd_in           : in     vl_logic_vector;
        sd_in           : in     vl_logic;
        ce              : in     vl_logic;
        data_valid      : out    vl_logic;
        load_taps       : in     vl_logic;
        taps_in         : in     vl_logic_vector;
        sinit           : in     vl_logic;
        ainit           : in     vl_logic;
        new_seed        : out    vl_logic;
        term_cnt        : out    vl_logic
    );
end lfsr_v2_0;