_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 39 行

library verilog;
use verilog.vl_types.all;
entity blkmemsp_v3_0 is
    generic(
        c_addr_width    : integer := 9;
        c_default_data  : string  := "0";
        c_depth         : integer := 512;
        c_enable_rlocs  : integer := 0;
        c_has_default_data: integer := 1;
        c_has_din       : integer := 1;
        c_has_en        : integer := 1;
        c_has_limit_data_pitch: integer := 0;
        c_has_nd        : integer := 0;
        c_has_rdy       : integer := 0;
        c_has_rfd       : integer := 0;
        c_has_sinit     : integer := 1;
        c_has_we        : integer := 1;
        c_limit_data_pitch: integer := 18;
        c_mem_init_file : string  := "null.mif";
        c_pipe_stages   : integer := 1;
        c_reg_inputs    : integer := 0;
        c_sinit_value   : string  := "0000";
        c_width         : integer := 32;
        c_write_mode    : integer := 2
    );
    port(
        dout            : out    vl_logic_vector;
        addr            : in     vl_logic_vector;
        din             : in     vl_logic_vector;
        en              : in     vl_logic;
        clk             : in     vl_logic;
        we              : in     vl_logic;
        sinit           : in     vl_logic;
        nd              : in     vl_logic;
        rfd             : out    vl_logic;
        rdy             : out    vl_logic
    );
end blkmemsp_v3_0;