_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 24 行

library verilog;
use verilog.vl_types.all;
entity vfft32_complex_mult_v2_0 is
    generic(
        a_width         : integer := 12;
        b_width         : integer := 12;
        max_mult_vgen_latency: integer := 4;
        max_complex_mult_latency: integer := 6;
        ascii_zero      : integer := 48
    );
    port(
        ar              : in     vl_logic_vector;
        ai              : in     vl_logic_vector;
        br              : in     vl_logic_vector;
        bi              : in     vl_logic_vector;
        clk             : in     vl_logic;
        ce              : in     vl_logic;
        start           : in     vl_logic;
        reset           : in     vl_logic;
        p_re            : out    vl_logic_vector;
        p_im            : out    vl_logic_vector
    );
end vfft32_complex_mult_v2_0;