_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 23 行

library verilog;
use verilog.vl_types.all;
entity mac_kdcm_v2_0 is
    generic(
        b_signed        : integer := 1;
        constant_datab  : integer := 3;
        constant_widthb : integer := 4;
        c_has_ce        : integer := 0;
        registered      : integer := 0;
        widtha          : integer := 9
    );
    port(
        dataa           : in     vl_logic_vector;
        datab           : in     vl_logic_vector;
        loadb           : in     vl_logic;
        signeda         : in     vl_logic;
        c               : in     vl_logic;
        ce              : in     vl_logic;
        busy            : out    vl_logic;
        product         : out    vl_logic_vector
    );
end mac_kdcm_v2_0;