_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 34 行

library verilog;
use verilog.vl_types.all;
entity c_mem_sp_block_v1_0 is
    generic(
        c_address_width : integer := 12;
        c_clk_polarity  : integer := 1;
        c_default_data  : string  := "0";
        c_depth         : integer := 4096;
        c_en_polarity   : integer := 1;
        c_generate_mif  : integer := 0;
        c_has_di        : integer := 1;
        c_has_do        : integer := 1;
        c_has_en        : integer := 1;
        c_has_rst       : integer := 1;
        c_has_we        : integer := 1;
        c_mem_init_file : string  := "null.mif";
        c_mem_init_radix: integer := 2;
        c_pipe_stages   : integer := 0;
        c_read_mif      : integer := 1;
        c_rst_polarity  : integer := 1;
        c_we_polarity   : integer := 1;
        c_width         : integer := 1
    );
    port(
        addr            : in     vl_logic_vector;
        di              : in     vl_logic_vector;
        clk             : in     vl_logic;
        we              : in     vl_logic;
        en              : in     vl_logic;
        rst             : in     vl_logic;
        do              : out    vl_logic_vector
    );
end c_mem_sp_block_v1_0;