_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 35 行

library verilog;
use verilog.vl_types.all;
entity pdafirvht is
    generic(
        antisymmetry    : integer := 0;
        cascade         : integer := 0;
        coefdata0       : integer := 1;
        coefdata1       : integer := 1;
        coefdata2       : integer := 1;
        coefdata3       : integer := 1;
        coefdata4       : integer := 1;
        coefdata5       : integer := 1;
        coefdata6       : integer := 1;
        coefdata7       : integer := 1;
        coefdata8       : integer := 1;
        coefdata9       : integer := 1;
        coef_width      : integer := 8;
        input_width     : integer := 8;
        number_of_taps  : integer := 8;
        output_width    : integer := 12;
        signed_input_data: integer := 1;
        symmetry        : integer := 1;
        trim_empty_roms : integer := 0;
        max_number_of_coeficients: integer := 10
    );
    port(
        data_in         : in     vl_logic_vector;
        data_out        : out    vl_logic_vector;
        c_m_i           : in     vl_logic_vector;
        c_d_o           : out    vl_logic_vector;
        c_m_o           : out    vl_logic_vector;
        ck              : in     vl_logic
    );
end pdafirvht;