_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 18 行

library verilog;
use verilog.vl_types.all;
entity bcount_up_ainit_v4 is
    generic(
        cnt_size        : integer := 6;
        init_val        : string  := "000000";
        c_enable_rlocs  : integer := 1;
        no              : integer := 0;
        yes             : integer := 1
    );
    port(
        init            : in     vl_logic;
        cen             : in     vl_logic;
        clk             : in     vl_logic;
        cnt             : out    vl_logic_vector
    );
end bcount_up_ainit_v4;