_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity or_a_b_v4 is
    port(
        a_in            : in     vl_logic;
        b_in            : in     vl_logic;
        or_out          : out    vl_logic
    );
end or_a_b_v4;