_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 17 行

library verilog;
use verilog.vl_types.all;
entity or_fd_v4 is
    generic(
        init_val        : string  := "0";
        no              : integer := 0;
        yes             : integer := 1
    );
    port(
        a_in            : in     vl_logic;
        b_in            : in     vl_logic;
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        q_out           : out    vl_logic
    );
end or_fd_v4;