_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 16 行

library verilog;
use verilog.vl_types.all;
entity gray_to_binary is
    generic(
        num_of_bits     : integer := 6;
        init_val        : string  := "";
        c_enable_rlocs  : integer := 1
    );
    port(
        bin_reg         : out    vl_logic_vector;
        grey_reg        : in     vl_logic_vector;
        reset           : in     vl_logic;
        clk             : in     vl_logic
    );
end gray_to_binary;